公开(公告)号：US20230132695A1

公开(公告)日：2023-05-04

申请号：US17906581

申请日：2021-01-26

申请人： Arm Limited

发明人： Jason PARKER ,  Yuval ELAD

IPC分类号： G06F12/14 ,  G06F12/1009 ,  G06F12/109

摘要： Processing circuitry (10) performs processing in one of at least three domains (82, 84, 86, 88). Address translation circuitry (16) translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces (61) selected based at least on the current domain. The domains include a root domain (82) for managing switching between other domains. The physical address spaces (61) include a root physical address space associated with the root domain (82), separate from physical address spaces associated with other domains.

公开(公告)号：US11620232B2

公开(公告)日：2023-04-04

申请号：US16367106

申请日：2019-03-27

申请人： International Business Machines Corporation

发明人： Andrew D. Baptist ,  Yogesh R. Vedpathak

IPC分类号： G06F12/10 ,  G06F12/1072 ,  G06F3/06 ,  G06F11/10 ,  G06F12/1081 ,  G06F12/109

摘要： A method begins by a storage unit of a dispersed storage network (DSN) receiving access requests which include a logical DSN address and a storage function. The method continues with a first processing module of the storage unit performing logical to physical address conversions of logical DSN addresses of the access requests to physical addresses of a plurality of main memories. For a first access request of the access requests, the method continues with the first processing module identifying a first main memory based on the physical address resulting from the physical address conversion. The method continues with the first processing module identifying a first processing thread of a plurality of processing threads based on allocation of the plurality of processing threads to the plurality of main memories. The method continues with the first processing thread executing tasks of the first access request to fulfill the first access request.

公开(公告)号：US20230098017A1

公开(公告)日：2023-03-30

申请号：US18076104

申请日：2022-12-06

申请人： Intel Corporation

发明人： Matthew Adiletta ,  Aaron Gorius ,  Myles Wilde ,  Michael Crocker

IPC分类号： H04L43/08 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16

摘要： Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

公开(公告)号：US11579910B2

公开(公告)日：2023-02-14

申请号：US16576860

申请日：2019-09-20

申请人： NetApp Inc.

发明人： Dean Alan Kalman

IPC分类号： G06F9/455 ,  G06F16/174 ,  G06F16/27 ,  G06F16/11 ,  G06F11/30 ,  G06F12/109

摘要： Techniques are provided for enforcing policies at a sub-logical unit number (LUN) granularity, such as at a virtual disk or virtual machine granularity. A block range of a virtual disk of a virtual machine stored within a LUN is identified. A quality of service policy object is assigned to the block range to create a quality of service workload object. A target block range targeted by an operation is identified. A quality of service policy of the quality of service policy object is enforced upon the operation using the quality of service workload object based upon the target block range being within the block range of the virtual disk.

公开(公告)号：US11513957B2

公开(公告)日：2022-11-29

申请号：US17027248

申请日：2020-09-21

申请人： Intel Corporation

发明人： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

IPC分类号： G06F12/0842 ,  G06F12/0893 ,  G06F12/109 ,  G06F12/0813 ,  G06F12/0831 ,  G06F9/455

摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

公开(公告)号：US11513890B1

公开(公告)日：2022-11-29

申请号：US17332727

申请日：2021-05-27

申请人： Western Digital Technologies, Inc.

发明人： Evgeny Mekhanik ,  Dudy David Avraham ,  Alexander Bazarsky

IPC分类号： G06F16/2453 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/901 ,  G06F9/4401 ,  G06F9/50 ,  H04L67/10 ,  G06F3/06 ,  G06F12/0893 ,  G06F16/17 ,  G06F11/10 ,  G06F12/109 ,  G06F16/23 ,  G06F16/242 ,  H03M7/30 ,  G06F16/2457 ,  G06F16/2458 ,  G06F16/27 ,  G06F7/24 ,  G06F11/30 ,  G06F11/07

摘要： A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command form a host device, collect environment data of the memory device, decode data associated with the read command, determine a bit error rate (BER) of the decoded data, compare the BER to a threshold, and determine whether the data associated with the read command is to be relocated. The environment data includes temperature, number of program/erase cycles, amount of grown defects, number of past relocations and time since last data relocation. The controller is further configured to dynamically adjust the threshold based on the collected environment data and an amount of time that has passed since a last relocation of the read command data.

公开(公告)号：US11494215B2

公开(公告)日：2022-11-08

申请号：US16490474

申请日：2017-03-31

申请人： Intel Corporation

发明人： Peng Huang ,  Liang Li ,  Xiaofeng Huang

IPC分类号： G06F9/455 ,  G06F9/48 ,  G06F12/109

摘要： Examples may include techniques to decrease a live migration time for a virtual machine (VM). Examples include selecting data to copy or not copy during a live migration of the VM from a source host server to a destination host server.

公开(公告)号：US11474857B1

公开(公告)日：2022-10-18

申请号：US16868479

申请日：2020-05-06

申请人： Amazon Technologies, Inc.

发明人： Sebastian Biemueller ,  Uwe Dannowski ,  Filippo Sironi ,  Barak Nirenberg

IPC分类号： H04L45/30 ,  G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  G06F12/109 ,  G06F13/38 ,  G06F13/28

摘要： As part of a compute instance migration, a compute instance which was executing at a first server begins execution at a second server before at least some state information of the compute instance has reached the second server. In response to a determination that a particular page of state information is not present at the second server, a migration manager running at one or more offload cards of the second server causes the particular page to be transferred to the second server via a network channel set up between the offload cards of both servers, and stores the page into main memory of the second server.

公开(公告)号：US11467982B2

公开(公告)日：2022-10-11

申请号：US16985898

申请日：2020-08-05

申请人： Intel Corporation

发明人： Rajesh P. Banginwar ,  Sumanth Naropanth ,  Sunil K. Notalapati Prabhakara ,  Surendra K. Singh ,  Arvind Mohan ,  Ravi L. Sahita ,  Rahil Malhotra ,  Aman Bakshi ,  Vasudevarao Kamma ,  Jyothi Nayak ,  Vivek Thakkar ,  Royston A. Pinto

IPC分类号： G06F12/14 ,  G06F9/48 ,  G06F21/53 ,  G06F9/455 ,  G06F21/57 ,  G06F12/109 ,  G06F12/02

摘要： A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The PPT may include a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application. The VMM may use a first extended page table (EPT) to translate a guest physical address (GPA) into a first host physical address (HPA) for the untrusted application. The VMM may use a second EPT to translate the GPA into a second HPA for the trusted application. The first and second EPTs may map the same GPA to different HPAs. Other embodiments are described and claimed.

公开(公告)号：US20220261168A1

公开(公告)日：2022-08-18

申请号：US17582416

申请日：2022-01-24

申请人： Ultrata, LLC

发明人： Steven J. Frank ,  Larry Reback

IPC分类号： G06F3/06 ,  G06F16/22 ,  G06F12/109

摘要： Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to a hardware-based processing node of an object memory fabric. The processing node may include a memory module storing and managing one or more memory objects, the one or more memory objects each include at least a first memory and a second memory, wherein: each memory object is created natively within the memory module, and each memory object is accessed using a single memory reference instruction without Input/Output (I/O) instructions; and a router configured to interface between a processor on the memory module and the one or more memory objects; wherein a set of data is stored within the first memory of the memory module; wherein the memory module dynamically determines that at least a portion of the set of data will be transferred from the first memory to the second memory; and wherein, in response to the determination that at least a portion of the set of data will be transferred from the first memory to the second memory, the router is configured to identify the portion to be transferred and to facilitate execution of the transfer.