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公开(公告)号：US20240361988A1
公开(公告)日：2024-10-31
申请号：US18342661
申请日：2023-06-27
申请人： Wistron Corporation
发明人： Jiun-In Guo , Wei-Chih Lin
摘要： Disclosed are an optimizing method and a computing system used for deep learning networks. The first data is obtained. The first data is quantized through the power of two quantization. The first data after the power of two quantization is the first format or the second format. The numbers of the first values in the first format or the second format is different. The second data is obtained. The second data is quantized through dynamic fixed-point quantization. A computation related to a deep learning network is performed on the quantized first data after the power of two quantization and the quantized second data after dynamic fixed-point quantization. Accordingly, the prediction precision could be increased, and the complexity of the model could be reduced.
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公开(公告)号：US20240361985A1
公开(公告)日：2024-10-31
申请号：US18603806
申请日：2024-03-13
发明人： Jinnan DING , Xiangtao WU
CPC分类号： G06F7/5318 , G06F7/50 , H03K19/21
摘要： Disclosed are an operation method of multiplier, an electronic device, and a storage medium. The method includes: determining a plurality of input data sets of the multiplier and an encoding manner for the multiplier; determining at least one low-order input data set in the plurality of input data sets; determining a carry compensation term corresponding to the at least one low-order input data set based on the at least one low-order input data set and the encoding manner; determining a target partial product array based on the carry compensation term corresponding to the at least one low-order input data set and the plurality of input data sets; and determining a product operation result for each input data set based on the target partial product array. According to this disclosure, multiplication operations with multiple precision may be implemented by using one multiplier, thereby reducing hardware resource consumption and hardware area.
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3.发明公开公开(公告)号：US20240304267A1
公开(公告)日：2024-09-12
申请号：US18670281
申请日：2024-05-21
发明人： Ryutaro YASUHARA , Satoru FUJII , Shunsaku MURAOKA
CPC分类号： G11C27/005 , G06F7/50 , G06F7/523 , G06N3/092 , H10B63/82
摘要： An artificial intelligence processing device includes: a first variable-resistance nonvolatile storage element and a second variable-resistance nonvolatile storage element having different properties and provided on a single substrate. When successive applications of a voltage pulse with a same polarity and a same voltage are made, a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the first variable-resistance nonvolatile storage element is less than a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the second variable-resistance nonvolatile storage element.
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公开(公告)号：US20240280747A1
公开(公告)日：2024-08-22
申请号：US18651225
申请日：2024-04-30
申请人： Celestial AI, Inc.
发明人： Martinus Bos , Philip Winterbottom
CPC分类号： G02B6/12004 , G02B6/12002 , G02B6/30 , G02B6/43 , G06F7/50 , G06F7/5318 , G06F7/5443 , G06N3/04 , G06N3/067 , G06N3/0675
摘要： Electro-photonic networks, including a plurality of processing elements connected by bidirectional photonic channels, suited for implementing neural-network models. Weights of the model may be preloaded into memory of the processing elements based on assignments of neural nodes to processing elements implementing them, and routers of the processing elements can be configured to stream activations between the processing elements based on a predetermined flow of activations in the model.
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公开(公告)号：US12067341B2
公开(公告)日：2024-08-20
申请号：US18358223
申请日：2023-07-25
发明人： Shih-Wei Peng , Jiann-Tyng Tzeng , Wei-Cheng Lin
IPC分类号： G06F7/50 , G03F1/36 , G03F1/70 , G06F30/398 , G09G3/3208 , H10K59/131 , H10K59/35 , H01L27/118 , H01L27/12
CPC分类号： G06F30/398 , G03F1/36 , G03F1/70 , G09G3/3208 , H10K59/131 , H10K59/353 , H01L2027/11881 , H01L27/1248
摘要： A complementary field effect transistor (CFET) structure includes a vertical stack of first and second transistors, wherein the first transistor includes a first channel extending in a first direction from a first source/drain (S/D) region to a second S/D region through a gate extending in a second direction perpendicular to the first direction and the second transistor includes a second channel extending in the first direction from a third S/D region to a fourth S/D region through the gate. A first conductive trace extends in the first direction over the gate, a first via extends from the first S/D region to the first conductive trace and is aligned with the third S/D region along the second direction, a second via extends from the fourth S/D region to the first conductive trace, and the first via has a first height greater than a second height of the second via.
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公开(公告)号：US20240232571A1
公开(公告)日：2024-07-11
申请号：US18094251
申请日：2023-01-06
申请人： Apple Inc.
发明人： Sung Hee Park
摘要： Embodiments of the present disclosure relate to decompressing a kernel for neural network operations in a neural processor circuit, using a look-up table (LUT) with each of its entries associated with a plurality of kernel coefficients. Index data in compressed kernel data includes indices that indicate entries in the LUT. During decompression, all kernel coefficients in entries as indicated by the indices of the index data are retrieved and assembled into the decompressed kernel. A block sparse mask may also be used to indicate a block of locations in the uncompressed kernel to be filled with zero values. Only one or more blocks of locations indicated by the block sparse mask to include at least one none-zero kernel coefficient may be populated with the kernel coefficients from the LUT while remaining blocks of locations are padded with zero.
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公开(公告)号：US12033090B2
公开(公告)日：2024-07-09
申请号：US17249312
申请日：2021-02-26
发明人： Yoshisato Sakai , Kotaro Endo
摘要： According to one embodiment, an information processing device includes a first storage and a first processing circuit. The first storage is configured to store constraint data which includes a constraint of a combinatorial optimization problem expressed in a formal language. The first processing circuit is configured to generate logical expression data from the constraint data and generate a penalty term data including a penalty term having a binary variable parameter by converting the logical expression data.
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8.发明公开公开(公告)号：US20240220201A1
公开(公告)日：2024-07-04
申请号：US17925367
申请日：2021-09-20
发明人： Brian C. Koziel , Rami El Khatib
摘要： A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result
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9.发明授权公开(公告)号：US12026479B2
公开(公告)日：2024-07-02
申请号：US17163494
申请日：2021-01-31
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
摘要： A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.
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公开(公告)号：US12019412B2
公开(公告)日：2024-06-25
申请号：US18214303
申请日：2023-06-26
IPC分类号： G05B13/02 , G06F7/50 , G06F7/523 , G06F17/14 , G06F17/16 , G06V10/44 , G06V10/762 , G06V10/764 , G06V10/82 , G06V10/94
CPC分类号： G05B13/027 , G06F7/50 , G06F7/523 , G06F17/141 , G06F17/16 , G06V10/454 , G06V10/7635 , G06V10/764 , G06V10/82 , G06V10/955
摘要： An autonomous module for processing stored data includes a multithreaded processor core (MPC) and a plurality of autonomous memories. Each of the plurality of autonomous memories has a memory bank, a data operator (DO) configured to implement a plurality of selectable memory behaviors, an autonomous memory operator (AMO) configured to implement a state machine to control the memory bank independently of the MPC, and at least one memory input/output (IO) port communicatively coupled with the memory bank, the AMO, and the DO. The at least one memory IO port is configured to receive a read instruction from the AMO, retrieve data from the memory bank, and send the data to the DO. The DO is configured to implement one of the plurality of selectable memory behaviors to update the data and send the updated data to the AMO via the at least one memory IO port.
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