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公开(公告)号:US20240363078A1
公开(公告)日:2024-10-31
申请号:US18523635
申请日:2023-11-29
发明人: HONG-KYU KIM
IPC分类号: G09G3/3266 , G09G3/20 , G09G3/3233
CPC分类号: G09G3/3266 , G09G3/2096 , G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2310/0286 , G09G2310/08
摘要: A gate driver includes M active stages configured to generate first through M-th carry signals and first through M-th gate signals based on clock signals, where M is an integer greater than or equal to 4, and K back dummy stages configured to generate (M+1)-th through (M+K)-th carry signals based on the clock signals, where K is an integer greater than or equal to 3. An N-th active stage of the M active stages discharges a control node of the N-th active stage based on an (N+3)-th carry signal, where N is an integer greater than or equal to 1, and is less than or equal to M. At least one back dummy stage of the K back dummy stages discharges a control node of the at least one back dummy stage based on a corresponding clock signal of the clock signals.
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公开(公告)号:US20240363066A1
公开(公告)日:2024-10-31
申请号:US18029356
申请日:2022-06-21
发明人: Song LIU , Yang ZHOU , Lu BAI , Junxiu DAI , Lingtong LI , Liheng WEI , Tianci CHEN
IPC分类号: G09G3/3233 , G09G3/00 , G09G3/3266
CPC分类号: G09G3/3233 , G09G3/006 , G09G3/3266 , G09G2310/0286 , G09G2310/0291 , G09G2310/08 , G09G2330/023 , G09G2330/12
摘要: A display substrate and a display device are provided, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes a pixel circuit, a scan drive circuit, a control drive circuit and a buffer drive circuit; the pixel circuit includes a node reset transistor, a writing transistor, a reset signal line connected to a control electrode of the node reset transistor, a scan signal line connected to a control electrode of the writing transistor, and a control signal line; reset signal lines of pixel circuits of first to K-th rows are electrically connected with the buffer drive circuit, reset signal lines of pixel circuits of (K+1)-th to N-th row are electrically connected with the scan drive circuit or the control drive circuit.
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公开(公告)号:US12125445B2
公开(公告)日:2024-10-22
申请号:US18208074
申请日:2023-06-09
发明人: Jung Kook Park , Dong Wan Park , Do Hyun Kang
IPC分类号: G09G3/3291 , G09G3/3266
CPC分类号: G09G3/3291 , G09G3/3266 , G09G2320/0626
摘要: A display device includes at least a first luminance range and a second luminance range which includes a luminance different from the first luminance range. In a boundary area of a second dimming range corresponding to the second luminance range and which is adjacent to a first dimming range corresponding to the first luminance range, a reference luminance emitted from a pixel is maintained as a first constant luminance value, and an off-duty number, which is the number of periods in which the pixel is turned off during one frame, is gradually increased by an emission control signal.
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公开(公告)号:US12125443B2
公开(公告)日:2024-10-22
申请号:US17981778
申请日:2022-11-07
发明人: Sungjin Hong , Chung Sock Choi , Hyewon Kim , Yoomin Ko , Sunho Kim , Juchan Park , Pilsuk Lee
IPC分类号: G09G3/3275 , G09G3/3266
CPC分类号: G09G3/3275 , G09G3/3266 , G09G2300/0452 , G09G2310/0272
摘要: A display panel includes a first display area and a second display area. A plurality of base pixel parts are disposed in the second display area, and each base pixel part includes “k” first color light emitting elements. A controller receives image signals, and the image signals include first image signals corresponding to the first display area and second image signals corresponding to the second display area. The second image signals are divided into a plurality of base signal parts respectively corresponding to the plurality of base pixel parts, and each base signal part includes “m*n” first color image signals. The controller generates color image data by rendering “p” color image signals of “m*n” color image signals included in a corresponding base signal part and “(m*n)−p” referenced image signals included in a referenced signal part adjacent to the corresponding base signal part.
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公开(公告)号:US20240347018A1
公开(公告)日:2024-10-17
申请号:US18613713
申请日:2024-03-22
发明人: Seiko AMANO , Hiroyuki MIYAKE
IPC分类号: G09G3/36 , G06F1/3234 , G06F3/038 , G09G3/3266 , G09G5/00 , G11C19/28 , H01L27/12
CPC分类号: G09G3/3677 , G06F1/3265 , G06F3/038 , G09G3/3266 , G11C19/28 , H01L27/124 , G09G5/008 , G09G2300/0809 , G09G2300/0871 , G09G2310/0205 , G09G2310/0248 , G09G2310/0286 , G09G2310/08 , G09G2320/0247 , G09G2330/021
摘要: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
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公开(公告)号:US12118947B2
公开(公告)日:2024-10-15
申请号:US18028710
申请日:2020-10-02
发明人: Nobuyuki Taya , Makoto Yokoyama , Naoki Ueda
IPC分类号: G09G3/3266 , G09G3/3233 , G11C19/28
CPC分类号: G09G3/3266 , G09G3/3233 , G11C19/287 , G09G2300/0819 , G09G2300/0852 , G09G2310/0286 , G09G2310/08 , G09G2320/041 , G09G2320/043
摘要: The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.
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公开(公告)号:US12118941B2
公开(公告)日:2024-10-15
申请号:US18350688
申请日:2023-07-11
申请人: LG Display Co., Ltd.
发明人: Jaeyong You
IPC分类号: G09G3/3233 , G09G3/3266 , G09G3/3291
CPC分类号: G09G3/3233 , G09G3/3266 , G09G3/3291 , G09G2330/028
摘要: A display device includes a display panel on which gate lines, data lines and subpixels are disposed; a gate driving circuit which drives the gate lines; and a data driving circuit which drives the data lines. Each of the subpixels includes: a light emitting device; a second transistor which has a first node, a second node that is a gate node, and a third node electrically connected to the light emitting device, and drives the light emitting device; a first transistor electrically connected between the third node and the data line; a third transistor electrically connected between the first node and the second node; and a fourth transistor electrically connected between the third node and the light emitting device. The third transistor performs a turn-off operation later than the first transistor, so that a voltage applied to the third node is transmitted to the second node via the first node.
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公开(公告)号:US20240331645A1
公开(公告)日:2024-10-03
申请号:US18742785
申请日:2024-06-13
申请人: LG DISPLAY CO., LTD.
发明人: Kyu Jin KIM , Seung Taek OH , Dong Gun LEE
IPC分类号: G09G3/34 , G09G3/3233 , G09G3/3266
CPC分类号: G09G3/3406 , G09G3/3233 , G09G3/3266 , G09G2300/0452 , G09G2300/0819 , G09G2300/0842 , G09G2310/08 , G09G2320/0626 , G09G2320/0686
摘要: A display device can include a display panel configured to display an input image across a first subpixel region and a second subpixel region, a display panel driver configured to supply pixel data of the input image to subpixels of the display panel, and a light source disposed under the display panel in an area overlapped by the second subpixel region. Also, the display device can further include a controller configured to drive the light source in an emission permitting section set within a non-driving period of a group of subpixels among the subpixels that are disposed in at least a portion of the second subpixel region, in which a scan pulse is supplied to subpixels in the first and second subpixel regions during the emission permitting section.
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公开(公告)号:US20240331640A1
公开(公告)日:2024-10-03
申请号:US18383545
申请日:2023-10-25
发明人: Huanxi ZHANG , Zhilin YANG , Shuyuan ZHANG
IPC分类号: G09G3/3258 , G09G3/32 , G09G3/3266 , G09G3/3291
CPC分类号: G09G3/3258 , G09G3/32 , G09G3/3266 , G09G3/3291 , G09G2310/0267 , G09G2310/0275 , G09G2310/08
摘要: The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a driving transistor and a data writing module. a driving timing of the pixel driving circuit includes a writing frame including a first data writing phase and a second data writing phase in sequence, the data voltage includes an active data voltage and a first data compensation voltage, the data writing module is configured to write the first data compensation voltage into the gate, the first electrode, and the second electrode of the driving transistor in the first data writing phase, and to write the active data voltage into the gate, the first electrode, and the second electrode of the driving transistor in the second data writing phase.
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公开(公告)号:US20240331609A1
公开(公告)日:2024-10-03
申请号:US18740424
申请日:2024-06-11
发明人: Haigang QING , Yunsheng XIAO
IPC分类号: G09G3/20 , G09G3/3266 , G11C19/28 , H10K71/00
CPC分类号: G09G3/2092 , G09G3/3266 , G09G2300/0408 , G09G2300/0426 , G09G2300/0809 , G09G2310/0286 , G09G2310/08 , G11C19/28 , H10K71/00
摘要: A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.
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