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    Circuits and methods for compensating a mismatch in a sense amplifier
    1.
    发明授权
    Circuits and methods for compensating a mismatch in a sense amplifier 有权

    公开(公告)号：US12080375B2

    公开(公告)日：2024-09-03

    申请号：US18232768

    申请日：2023-08-10

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Ku-Feng Lin ,  Yu-Der Chih ,  Yi-Chun Shih ,  Chia-Fu Lee

    IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C11/14 ,  G11C13/00 ,  H01L27/10

    CPC分类号： G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

    摘要： Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    Circuits and methods for compensating a mismatch in a sense amplifier
    2.
    发明授权
    Circuits and methods for compensating a mismatch in a sense amplifier 有权

    公开(公告)号：US11783873B2

    公开(公告)日：2023-10-10

    申请号：US17737734

    申请日：2022-05-05

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Ku-Feng Lin ,  Yu-Der Chih ,  Yi-Chun Shih ,  Chia-Fu Lee

    IPC分类号： G11C7/06 ,  G11C11/14 ,  G11C7/08 ,  G11C13/00 ,  H01L27/10

    CPC分类号： G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

    摘要： Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    Display device
    5.
    发明授权
    Display device 有权

    公开(公告)号：US10997933B2

    公开(公告)日：2021-05-04

    申请号：US16744638

    申请日：2020-01-16

    申请人： Japan Display Inc.

    发明人： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Yutaka Ozawa ,  Masaya Tamaki

    IPC分类号： G09G3/36 ,  H04N5/3745 ,  G09G5/39 ,  G11C11/16 ,  G11C11/14

    摘要： A display device is provided and includes sub-pixels each including a sub-pixel electrode, and a first and second memory; a clock signal output circuit configured to, based on a reference clock signal, output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a memory selection circuit configured to select all of the first memories included in all the sub-pixels or all of the second memories included in all the sub-pixels in synchronization with the selected clock signal; a common electrode facing all of the sub-pixel electrodes; and a common-electrode driving circuit configured to provide a common potential to the common electrode, wherein the common potential is inverted in synchronization with the reference clock signal, wherein the sub-pixel electrode is driven based on sub-pixel data stored in the selected one of the memories to display an image.

    Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer
    6.
    发明授权
    Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer 有权

    公开(公告)号：US10784437B2

    公开(公告)日：2020-09-22

    申请号：US16121480

    申请日：2018-09-04

    申请人： SPIN MEMORY, Inc.

    发明人： Satoru Araki

    IPC分类号： H01L43/02 ,  H01L43/10 ,  G11C11/14 ,  H01L43/12 ,  H01L27/22 ,  H01L21/822

    摘要： A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.

    Display device
    7.
    发明授权
    Display device 有权

    公开(公告)号：US10553167B2

    公开(公告)日：2020-02-04

    申请号：US16020055

    申请日：2018-06-27

    申请人： Japan Display Inc.

    发明人： Yutaka Mitsuzawa ,  Takayuki Nakao ,  Yutaka Ozawa ,  Masaya Tamaki

    IPC分类号： G09G3/36 ,  G09G5/39 ,  H04N5/3745 ,  G11C11/16 ,  G11C11/14

    摘要： A display device includes: a plurality of sub-pixels each including a memory block; a clock signal output circuit configured to output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a plurality of memory selection line groups provided for respective rows; a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from a plurality of memories in each of the memory blocks; a common electrode to which a common potential common to the sub-pixels is supplied; and a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential.