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1.发明授权公开(公告)号：US12002509B2
公开(公告)日：2024-06-04
申请号：US17756315
申请日：2021-07-02
发明人： Feng Zhang , Qirui Ren
CPC分类号： G11C13/004 , G11C13/0059 , G11C2013/0045
摘要： A data readout circuit of a RRAM includes: an adaptive current sense amplifier (CSA) and a reference current generator, the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current according to the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare the size of the reference current and that of the bit-line current so as to read out stored data. The present disclosure can improve the problem of data readout error due to the degradation of high resistance state of the RRAM.
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2.发明公开公开(公告)号：US20230368829A1
公开(公告)日：2023-11-16
申请号：US18355510
申请日：2023-07-20
发明人： Jack Liu , Charles Chew-Yuen Young
CPC分类号： G11C11/1673 , G11C11/1693 , H01F10/3254 , G11C11/161 , G11C11/15 , G11C11/02 , H10B61/22 , H10N50/80
摘要： Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.
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3.发明授权公开(公告)号：US11798607B2
公开(公告)日：2023-10-24
申请号：US17524125
申请日：2021-11-11
发明人： Jack Liu , Charles Chew-Yuen Young
CPC分类号： G11C11/1673 , G11C11/02 , G11C11/15 , G11C11/161 , G11C11/1693 , H01F10/3254 , H10B61/22 , H10N50/80
摘要： Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.
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4.发明授权公开(公告)号：US11790967B2
公开(公告)日：2023-10-17
申请号：US17420053
申请日：2020-05-15
申请人： TDK CORPORATION
发明人： Shogo Yamada , Tatsuo Shibata , Yugo Ishitani
IPC分类号： G11C11/16 , H01L29/82 , H10N50/10 , H01L27/105 , G11C11/15
CPC分类号： G11C11/161 , G11C11/1675 , H01L29/82 , H10N50/10 , G11C11/15 , H01L27/105
摘要： A magnetic domain wall displacement element includes a first ferromagnetic layer, a second ferromagnetic layer extending in a second direction and magnetically recordable, a nonmagnetic layer, and a first conductive part having a first intermediate layer and a second conductive part having a second intermediate layer, in which the first intermediate layer is sandwiched between first and second magnetization regions and exhibiting first and second magnetization directions, the second intermediate layer is sandwiched between a third magnetization region and exhibiting the second magnetization direction and a fourth magnetization region exhibiting the first magnetization direction in the first direction, and an area of the first magnetization region is larger than an area of the second magnetization region and an area of the third magnetization region is smaller than an area of the fourth magnetization region in a cross section in the first direction and the second direction.
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公开(公告)号：US11756618B1
公开(公告)日：2023-09-12
申请号：US17361304
申请日：2021-06-28
IPC分类号： G06F12/12 , G11C14/00 , G11C11/15 , G06F12/128 , G06F12/0897 , G11C13/00 , G06F3/06 , G06F12/0815
CPC分类号： G11C14/0045 , G06F12/0897 , G06F12/128 , G11C11/15 , G06F3/06 , G06F12/0815 , G06F2212/1032 , G06F2212/202 , G06F2212/214 , G11C13/0002
摘要： A log structure is created in persistent memory using hardware support in memory controller or software supported with additional instructions. Writes to persistent memory locations are streamed to the log and written to their corresponding memory location in cache hierarchy. An added victim cache for persistent memory addresses catches cache evictions, which would corrupt open transactions. On the completion of a group of atomic persistent memory operations, the log is closed and the persistent values in the cache can be copied to their source persistent memory location and the log cleaned.
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公开(公告)号：US11735234B2
公开(公告)日：2023-08-22
申请号：US17557825
申请日：2021-12-21
发明人： Daniele Vimercati , Xinwei Guo
CPC分类号： G11C7/062 , G11C11/15 , G11C11/1657 , H03F3/45076
摘要： Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.
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公开(公告)号：US20220108158A1
公开(公告)日：2022-04-07
申请号：US17061798
申请日：2020-10-02
摘要： An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.
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公开(公告)号：US11264565B2
公开(公告)日：2022-03-01
申请号：US16843708
申请日：2020-04-08
申请人： TOHOKU UNIVERSITY
发明人： Hiroaki Honjo , Tetsuo Endoh , Hideo Sato , Shoji Ikeda
摘要： An object of the invention is to provide a magnetoresistance effect element which includes a reference layer having three or more magnetic layers and which improves a thermal stability factor Δ by decreasing a write error rate using an element structure that enables a wide margin to be secured between a current at which magnetization of the reference layer is reversed and a writing current Ic of a recording layer and by reducing an effect of a stray magnetic field from the reference layer.
The magnetoresistance effect element includes: a first recording layer (A1); a first non-magnetic layer (11); and a first reference layer (B1), wherein the first reference layer (B1) including n-number of a plurality of magnetic layers (21, 22, . . . , 2n) and (n−1)−number of a plurality of non-magnetic insertion layers (31, 32, . . . 3(n−1)) adjacently sandwiched by each of the plurality of magnetic layers, where n≥3.-
公开(公告)号：US11233193B2
公开(公告)日：2022-01-25
申请号：US16862598
申请日：2020-04-30
申请人： Japan Science and Technology Agency , National Institute of Advanced Industrial Science and Technology
发明人： Shinji Yuasa
IPC分类号： H01L21/02 , H01L21/00 , H01L43/10 , H01F10/13 , G11C11/15 , H01L49/02 , H01L27/11507 , B82Y25/00 , G11C11/16 , H01L27/22 , H01L43/08 , H01L43/12 , H01F10/32 , H01L43/02 , B82Y10/00
摘要： A method of manufacturing a magnetoresistive random access memory (MRAM). The method includes forming a first CoFeB layer of the MTJ devices, the first CoFeB layer being amorphous and forming a magnesium oxide (MgO) layer of the MTJ devices over the first CoFeB layer. Further, there is a forming of a second CoFeB layer of the MTJ devices, the second CoFeB layer being amorphous over the MgO layer, and annealing the MTJ devices. The first and second CoFeB layers are crystallized by the annealing, and the MgO layer is poly-crystalline in which a (001) crystal plane is preferentially oriented.
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公开(公告)号：US10964387B2
公开(公告)日：2021-03-30
申请号：US16800081
申请日：2020-02-25
发明人： Artur Antonyan
摘要： A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.
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