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公开(公告)号：US12106812B2
公开(公告)日：2024-10-01
申请号：US17819826
申请日：2022-08-15
发明人： Yu-Chung Lien , Zhenming Zhou , Tomer Tzvi Eliash
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/24 , G11C16/32
摘要： Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.
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公开(公告)号：US12106797B2
公开(公告)日：2024-10-01
申请号：US17859153
申请日：2022-07-07
发明人： Seong Ook Jung , In Jun Jung , Tae Hyun Kim
IPC分类号： G11C11/34 , G11C11/408 , G11C11/4093 , G11C11/4094 , H03K19/017
CPC分类号： G11C11/4093 , G11C11/4085 , G11C11/4094 , H03K19/01742
摘要： A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.
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公开(公告)号：US12082409B2
公开(公告)日：2024-09-03
申请号：US17674289
申请日：2022-02-17
IPC分类号： G11C11/34 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27 , G11C16/04 , H10B41/35 , H10B43/35
摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers having channel-material strings therein. Walls are formed above insulating material that is directly above the channel-material strings. Void space is laterally-between immediately-adjacent of the walls and that comprises a longitudinal outline of individual digitlines to be formed. Spaced openings are in the insulating material directly below the void space. Relative to the walls, a conductive metal nitride is selectively deposited in the void space, in the spaced openings, and atop the insulating material laterally-between the walls and the spaced openings to form a lower portion of the individual digitlines laterally-between the immediately-adjacent walls. The conductive metal nitride that is in individual of the spaced openings is directly electrically coupled to individual of the channel-material strings. A conductive material is formed in the void space directly above and directly electrically coupled to the lower portion of the individual digitlines to form an upper portion thereof. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US11972803B2
公开(公告)日：2024-04-30
申请号：US17571124
申请日：2022-01-07
发明人： Yu-Chung Lien , Fanqi Wu , Jiahui Yuan
CPC分类号： G11C16/102 , G11C7/1048 , G11C16/08 , G11C16/26 , G11C16/30
摘要： A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.
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公开(公告)号：US11961574B2
公开(公告)日：2024-04-16
申请号：US17575393
申请日：2022-01-13
申请人： SK hynix Inc.
发明人： June Young Choi , Un Sang Lee
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.
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公开(公告)号：US11955189B2
公开(公告)日：2024-04-09
申请号：US18075027
申请日：2022-12-05
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/26 , G11C29/42 , H03K19/02
摘要： Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios.
The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.-
公开(公告)号：US11948646B2
公开(公告)日：2024-04-02
申请号：US18305654
申请日：2023-04-24
申请人： Kioxia Corporation
发明人： Kosuke Yanagidaira , Mario Sako
CPC分类号： G11C16/26 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30
摘要： A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.
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公开(公告)号：US11948640B2
公开(公告)日：2024-04-02
申请号：US17371568
申请日：2021-07-09
申请人： Kioxia Corporation
发明人： Makoto Iwai , Hiroshi Nakamura
CPC分类号： G11C16/0483 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/06 , G11C16/08 , G11C16/26 , G11C16/3436 , G11C16/3454 , G11C16/3459
摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
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公开(公告)号：US11894074B2
公开(公告)日：2024-02-06
申请号：US17469812
申请日：2021-09-08
申请人： Kioxia Corporation
发明人： Koji Kato
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3404
摘要： A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.
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10.发明授权公开(公告)号：US11889694B2
公开(公告)日：2024-01-30
申请号：US17397846
申请日：2021-08-09
IPC分类号： G11C11/34 , H10B43/27 , G11C5/06 , H01L23/522 , G11C8/14 , H01L23/528 , H10B41/10 , H10B41/35
CPC分类号： H10B43/27 , G11C5/063 , G11C8/14 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/35
摘要： A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.
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