公开(公告)号：US20250037746A1

公开(公告)日：2025-01-30

申请号：US18680395

申请日：2024-05-31

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US20240212742A1

公开(公告)日：2024-06-27

申请号：US18595293

申请日：2024-03-04

Applicant: LONGITUDE LICENSING LIMITED

Inventor： Chikara Kondo

IPC: G11C11/409 ,  G11C7/24 ,  G11C8/12 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/52

CPC classification number: G11C11/409 ,  G11C7/24 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/52 ,  G11C8/12

Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.

公开(公告)号：US12002540B2

公开(公告)日：2024-06-04

申请号：US18214466

申请日：2023-06-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C29/02 ,  G11C5/02 ,  G11C5/04 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C11/4063 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US11995008B2

公开(公告)日：2024-05-28

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16 ,  G11C11/4063

CPC classification number: G06F13/1642 ,  G11C11/4063

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

公开(公告)号：US20240170040A1

公开(公告)日：2024-05-23

申请号：US18460992

申请日：2023-09-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YUKI MIURA ,  MOEHA SHIBUYA ,  SAAYA IZUMI

IPC: G11C11/4063 ,  H01L23/528

CPC classification number: G11C11/4063 ,  H01L23/5283 ,  H01L23/5286

Abstract: An apparatus that includes first, second, third and fourth circuit regions arranged in a first direction in numerical order. The first circuit region includes a first global power supply line extending in a second direction vertical to the first direction and a first local power supply line, the first local power supply line being branched from the first global power supply line and extending in the first direction across the second, third and fourth regions. The third circuit region includes a first power switch coupled between the first local power supply line and an internal power supply line extending in the first direction across the first, second, third and fourth regions. Each of the second and fourth regions includes a circuit coupled to the first local power supply line and an additional circuit coupled to the internal power supply line.

公开(公告)号：US11922994B2

公开(公告)日：2024-03-05

申请号：US17872771

申请日：2022-07-25

Applicant: LONGITUDE LICENSING LIMITED

Inventor： Chikara Kondo

IPC: G11C7/00 ,  G11C7/24 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/408 ,  G11C11/409 ,  G11C29/52 ,  G11C8/12

CPC classification number: G11C11/409 ,  G11C7/24 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/52 ,  G11C8/12

Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.

公开(公告)号：US11875840B2

公开(公告)日：2024-01-16

申请号：US17527908

申请日：2021-11-16

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Hae Rang Choi ,  Sungjoo Yoo

IPC: G11C11/54 ,  G11C11/4091 ,  G06F7/50 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/4063

CPC classification number: G11C11/4091 ,  G06F7/50 ,  G11C7/1051 ,  G11C11/4063 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/54 ,  G11C7/1006

Abstract: A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.

公开(公告)号：US11804167B2

公开(公告)日：2023-10-31

申请号：US17954760

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joong Min Ra

IPC: G06F13/16 ,  G11C11/4076 ,  G06F3/06 ,  G09G5/00 ,  G09G3/20 ,  G06F3/041 ,  G11C11/4063 ,  G06F13/00 ,  G11C7/10 ,  G06F3/14

CPC classification number: G09G3/2096 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/0656 ,  G06F13/00 ,  G06F13/1647 ,  G06F13/1657 ,  G09G5/003 ,  G11C7/1087 ,  G11C11/4063 ,  G11C11/4076 ,  G06F3/14 ,  G09G2310/0264 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/08 ,  G09G2360/12 ,  G09G2360/18

Abstract: A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.

公开(公告)号：US11710063B2

公开(公告)日：2023-07-25

申请号：US17967559

申请日：2022-10-17

Applicant: Google LLC

Inventor： Craig Gidney

IPC: H04B10/00 ,  G06N10/00 ,  G11C11/4063 ,  G06F7/48 ,  G06F7/72 ,  G06F7/505 ,  G06F17/10 ,  H04B10/70 ,  H04J14/00

CPC classification number: G06N10/00 ,  G06F7/4824 ,  G06F7/505 ,  G06F7/5057 ,  G06F7/72 ,  G06F17/10 ,  G11C11/4063 ,  H04B10/70

Abstract: Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

公开(公告)号：US20230177373A1

公开(公告)日：2023-06-08

申请号：US18101522

申请日：2023-01-25

Applicant: Google LLC

Inventor： Craig Gidney ,  Austin Greig Fowler

IPC: G06N10/00 ,  G11C11/4063 ,  G06F7/48 ,  G06F7/72 ,  G06F7/505 ,  G06F17/10 ,  H04B10/70

CPC classification number: G06N10/00 ,  G06F7/72 ,  G06F7/505 ,  G06F7/4824 ,  G06F7/5057 ,  G06F17/10 ,  G11C11/4063 ,  H04B10/70

Abstract: Methods and apparatus for performing surface code computations using Auto-CCZ states. In one aspect, a method for implementing a delayed choice CZ operation on a first and second data qubit using a quantum computer includes: preparing a first and second routing qubit in a magic state; interacting the first data qubit with the first routing qubit and the second data qubit with the second routing qubit using a first and second CNOT operation, where the first and second data qubits act as controls for the CNOT operations; if a received first classical bit represents an off state: applying a first and second Hadamard gate to the first and second routing qubit; measuring the first and second routing qubit using Z basis measurements to obtain a second and third classical bit; and performing classically controlled fixup operations on the first and second data qubit using the second and third classical bits.