公开(公告)号：US20240363531A1

公开(公告)日：2024-10-31

申请号：US18626935

申请日：2024-04-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Soyeon Kim ,  Hoyoung Tang ,  Taehyung Kim

IPC分类号： H01L23/528 ,  G11C5/06 ,  G11C11/419 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC分类号： H01L23/5283 ,  G11C5/063 ,  G11C11/419 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H10B10/125

摘要： Provided is an integrated circuit including a cell array disposed on a substrate and including a plurality of bit cells, a row decoder including a plurality of word line drivers each providing a plurality of word line signals to the cell array, a backside wiring layer disposed on a back side of the substrate to overlap the row decoder and providing power to the plurality of word line drivers, and a plurality of backside contacts between the row decoder and the backside wiring layer. Each of the plurality of backside contacts extends from a source of at least one transistor included in each of the plurality of word line drivers to the backside wiring layer.

公开(公告)号：US12119051B2

公开(公告)日：2024-10-15

申请号：US17884861

申请日：2022-08-10

申请人： Micron Technology, Inc.

发明人： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/1015 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/227 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483 ,  G11C2207/2281

摘要： Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US20240341074A1

公开(公告)日：2024-10-10

申请号：US18749271

申请日：2024-06-20

申请人： Socionext Inc.

发明人： Masanobu HIROSE ,  Yasunori MURASE

IPC分类号： H10B10/00 ,  G11C11/412 ,  G11C11/419

CPC分类号： H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H10B10/18

摘要： Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

公开(公告)号：US12114473B2

公开(公告)日：2024-10-08

申请号：US17828123

申请日：2022-05-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhon-Jhy Liaw

IPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H10B10/00 ,  G11C8/08 ,  G11C8/16

CPC分类号： H10B10/18 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C8/16

摘要： Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

公开(公告)号：US20240331768A1

公开(公告)日：2024-10-03

申请号：US18619699

申请日：2024-03-28

申请人： STMicroelectronics International N.V.

发明人： Praveen Kumar VERMA ,  Ashfaque AHMED

IPC分类号： G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C11/418

摘要： An electronic device includes a memory and includes a plurality of word lines selectively driven by a decoder, with each pair of adjacent word lines having an underdrive circuit coupled therebetween. That underdrive circuit includes first and second transistors source/drain coupled in series with one another between the pair of adjacent word lines, the first and second transistors being replicas of a pull-down transistor and a pass gate transistor of bitcells the memory. One of the first and second transistors has its gate driven by a supply voltage and the other of the first and second transistor has its gate driven by a first read assist control signal.

公开(公告)号：US20240331765A1

公开(公告)日：2024-10-03

申请号：US18741051

申请日：2024-06-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC分类号： G11C11/412 ,  G11C11/419 ,  H10B10/00

CPC分类号： G11C11/412 ,  G11C11/419 ,  H10B10/12

摘要： Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US12106801B2

公开(公告)日：2024-10-01

申请号：US17858376

申请日：2022-07-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C5/02 ,  G11C7/10 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C5/025 ,  G11C7/1096 ,  G11C7/12

摘要： An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

公开(公告)号：US12094528B2

公开(公告)日：2024-09-17

申请号：US17833852

申请日：2022-06-06

申请人： QUALCOMM Incorporated

发明人： Dhvani Sheth ,  Hochul Lee ,  Anil Chowdary Kota ,  Chulmin Jung

IPC分类号： G11C29/14 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US20240304222A1

公开(公告)日：2024-09-12

申请号：US18670302

申请日：2024-05-21

申请人： Nuvoton Technology Corporation Japan

发明人： Atsushi MOTOTANI

IPC分类号： G11C5/14 ,  G11C11/419

CPC分类号： G11C5/148 ,  G11C11/419

摘要： A semiconductor memory device includes memory cells, a first power supply line, a second power supply line, a first transistor and a second transistor that are connected in parallel between the first power supply line and the second power supply line, and a control circuit. In accordance with a first signal for switching between a first mode and a second mode, the control circuit (i) switches off the first transistor and the second transistor in the period of the second mode and (ii) switches on the first transistor when switching from the second mode to the first mode is performed and switches on the second transistor after the first transistor is switched on, the first mode being a mode for supplying the power supply voltage to the memory cells, the second mode being a mode for not supplying the power supply voltage to memory cells.

公开(公告)号：US12087730B1

公开(公告)日：2024-09-10

申请号：US17654564

申请日：2022-03-11

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/419 ,  H01L25/065 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L25/0652 ,  G11C11/221 ,  G11C11/419 ,  H01L28/55 ,  H10B12/20 ,  H10B12/48

摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.