公开(公告)号：US20240363176A1

公开(公告)日：2024-10-31

申请号：US18638788

申请日：2024-04-18

申请人： Kioxia Corporation

发明人： Viktoria Diana SCHLYKOW ,  Reika TANAKA

IPC分类号： G11C16/34 ,  G11C11/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  H10B43/27 ,  H10B51/20

CPC分类号： G11C16/3404 ,  G11C11/223 ,  G11C11/2275 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H10B43/27 ,  H10B51/20

摘要： A semiconductor memory device of embodiments includes a semiconductor layer, a gate electrode layer, memory cells each including a gate insulating layer containing Si, O, and N, and a control circuit. The control circuit performs a write operation and an erase operation on the memory cells. The control circuit determine whether or not the number of times of execution of the erase operation on the memory cells has reached a predetermined number of times. When the number has reached the predetermined number of times, the control circuit perform first processing and second processing on the memory cells. The first processing applies a voltage with the same polarity as that in the write operation to the gate electrode layer with a pulse width larger than that in the write operation. The second processing applies a voltage with a polarity opposite to that in the write operation to the gate electrode layer.

公开(公告)号：US20240363170A1

公开(公告)日：2024-10-31

申请号：US18363518

申请日：2023-08-01

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.,

发明人： Naoto NORIZUKI ,  Hiroki YABE

IPC分类号： G11C16/16 ,  G11C16/04 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00

CPC分类号： G11C16/16 ,  G11C16/0483 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A semiconductor device includes a plurality of memory blocks and a bit-line-bias block. A source-drain erase bias voltage is applied between a source line and a bit lines through the bit-line-bias block during an erase operation.

公开(公告)号：US12131785B2

公开(公告)日：2024-10-29

申请号：US17829837

申请日：2022-06-01

申请人： Intel NDTM US LLC

发明人： Chao Zhang ,  Krishna Parat ,  Richard Fastow ,  Ricardo Basco ,  Xin Sun ,  Heonwook Kim ,  Zhan Liu

IPC分类号： G11C16/08 ,  G11C7/04 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349

摘要： Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

公开(公告)号：US12100459B2

公开(公告)日：2024-09-24

申请号：US18333661

申请日：2023-06-13

申请人： KIOXIA CORPORATION

发明人： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC分类号： G11C16/04 ,  G06F5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC分类号： G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

摘要： A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US12087364B2

公开(公告)日：2024-09-10

申请号：US17547856

申请日：2021-12-10

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masafumi Hayakawa

IPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/3445

摘要： A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed.

公开(公告)号：US20240296891A1

公开(公告)日：2024-09-05

申请号：US18358635

申请日：2023-07-25

申请人： Western Digital Technologies, Inc.

发明人： Ming Wang ,  Liang Li ,  Xuan Tian

IPC分类号： G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

摘要： Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

公开(公告)号：US12080772B2

公开(公告)日：2024-09-03

申请号：US18483466

申请日：2023-10-09

申请人： SK hynix Inc.

发明人： Sung Kun Park ,  Jae Young Song

IPC分类号： H01L29/423 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41

CPC分类号： H01L29/42328 ,  G11C16/16 ,  G11C16/26 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  G11C16/3427

摘要： A non-volatile memory device may include a substrate, a first floating gate, a second floating gate, a third floating gate and a fourth floating gate. The substrate may include an active region. The first to fourth floating gates may be formed on the substrate. The first to fourth floating gates may be radially arranged to be partially overlapped with the active region. The first floating gate and the third floating gate may face each other in a first direction. The first floating gate and the third floating gate may have asymmetrically planar shapes. The first floating gate and the second floating gate may face each other in a second direction substantially perpendicular to the first direction. The first floating gate and the second floating gate may have asymmetrically planar shapes. The third floating gate and the fourth floating gate may face each other in the second direction. The third floating gate and the fourth floating gate may have asymmetrically planar shapes. The fourth floating gate and the second floating gate may face each other in the first direction. The fourth floating gate and the second floating gate may have asymmetrically planar shapes.

公开(公告)号：US20240290406A1

公开(公告)日：2024-08-29

申请号：US18655700

申请日：2024-05-06

申请人： Micron Technology, Inc.

发明人： Rainer Frank BONITZ

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C16/345

摘要： A controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. The wear leveling pool includes a plurality of memory blocks of the memory. The controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. A first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.

公开(公告)号：US20240282394A1

公开(公告)日：2024-08-22

申请号：US18231127

申请日：2023-08-07

申请人： SK hynix Inc.

发明人： Chang Beom WOO

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

摘要： Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory strings, a peripheral circuit configured to perform an erase operation and a program operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation and the program operation on the memory block, wherein the control logic is configured to control the peripheral circuit to perform an abnormally injected electron removal operation that removes abnormally injected electrons trapped in a charge storage layer of a plurality of memory cells included in the memory block after the erase operation has been completed.

公开(公告)号：US12068042B2

公开(公告)日：2024-08-20

申请号：US17544260

申请日：2021-12-07

申请人： SK keyfoundry Inc.

发明人： Jin Hyung Kim ,  Sung Bum Park ,  Kee Sik Ahn

IPC分类号： G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

CPC分类号： G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

摘要： A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.