公开(公告)号：US20230140746A1

公开(公告)日：2023-05-04

申请号：US17828480

申请日：2022-05-31

申请人： SK hynix Inc.

发明人： In Jung

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26

摘要： A memory system comprises a memory device including plural memory blocks, and a controller coupled to the memory device. The controller controls the memory device to read a first group including plural data items and a parity associated with the plural data items from first locations in the plural memory blocks. The controller generates a new parity when the plural data items and the parity include plural errors, substitute one of the plural errors with the new parity and another of the plural errors with dummy data. The controller controls the memory device to program a second group including the new parity and the dummy data in second locations in the plural memory blocks. The second locations are different from the first locations.

公开(公告)号：US20230140731A1

公开(公告)日：2023-05-04

申请号：US17668392

申请日：2022-02-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huai-Ying Huang ,  Yu-Ming Lin

IPC分类号： H01L27/11 ,  G11C11/4091 ,  H01L27/108 ,  G11C11/419 ,  G11C16/26 ,  H01L27/11526 ,  H01L27/11573

摘要： A semiconductor device includes a semiconductor substrate, ground level circuitry, a plurality of stacked memory arrays and a plurality of sense amplifier units. The ground level circuitry is disposed on the semiconductor substrate. The stacked memory arrays are disposed at an elevated level over the ground level circuitry. The sense amplifier units are disposed on the semiconductor substrate and electrically coupled to the stacked memory arrays, wherein at least a portion of each of the sense amplifier units is disposed at the elevated level over the ground level circuitry.

公开(公告)号：US20230126507A1

公开(公告)日：2023-04-27

申请号：US17682602

申请日：2022-02-28

申请人： SK hynix Inc.

发明人： Sung Hun KIM ,  Beom Ju SHIN

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F1/30 ,  G11C16/10 ,  G11C16/26

摘要： A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.

公开(公告)号：US11636906B2

公开(公告)日：2023-04-25

申请号：US17369393

申请日：2021-07-07

申请人： SK hynix Inc.

发明人： Soo Yeol Chai

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26

摘要： Provided herein is a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells, and a peripheral circuit configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a program operation, wherein, during a verify operation included in the program operation, the peripheral circuit may be configured to allow a selected word line, among the plurality of word lines, to float, and may decrease a potential of the selected word line to a pre-level by decreasing potentials of adjacent word lines to the selected word line.

公开(公告)号：US11636899B2

公开(公告)日：2023-04-25

申请号：US17381359

申请日：2021-07-21

申请人： SK hynix Inc.

发明人： Sung Hyun Hwang ,  Jin Haeng Lee

IPC分类号： G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C16/08

摘要： Provided herein may be a memory device capable of completing program operations for multiple pages in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation and a second program operation and control logic configured to control the peripheral circuit to receive least significant bit (LSB) page data of a page adjacent to a selected page, center significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page from a memory controller, and program the LSB page data of the page adjacent to the page adjacent to the selected page and to obtain LSB page data from the selected page, previously stored in the selected page, and program the LSB page data, the CSB page data and the MSB page data of the selected page to the selected page.

公开(公告)号：US11636892B2

公开(公告)日：2023-04-25

申请号：US17346171

申请日：2021-06-11

申请人： Samsung Electronics Co., Ltd.

发明人： Minseok Kim ,  Hyunggon Kim

IPC分类号： G11C16/08 ,  G11C11/4091 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/04 ,  G11C11/4076 ,  G11C11/4099 ,  G11C16/26

摘要： In a method of counting the number of memory cells in a nonvolatile memory device, a measurement range and a plurality of measurement intervals of a measurement window for a cell counting operation are set to a first range and a plurality of first intervals, respectively. The plurality of measurement intervals are included in the measurement range. A first sensing operation is performed on first memory cells included in a first region of a memory cell array based on the measurement window. A first shifting operation for shifting the measurement window is performed while a width of the measurement range and a width of each of the plurality of measurement intervals are maintained. A second sensing operation is performed on the first memory cells based on the measurement window shifted by the first shifting operation. A final count value for the first memory cells is obtained based on a result of the first sensing operation and a result of the second sensing operation.

公开(公告)号：US20230122275A1

公开(公告)日：2023-04-20

申请号：US18083992

申请日：2022-12-19

申请人： MICRON TECHNOLOGY, INC.

发明人： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Xiangang Luo ,  Peter Feeley ,  Devin M. Batutis ,  Jiangang Wu ,  Sampath K. Ratnam ,  Shane Nowell ,  Karl D. Schuh

IPC分类号： G11C29/50 ,  G06F12/02 ,  G11C16/26 ,  G11C29/02 ,  G11C7/10

摘要： A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

公开(公告)号：US20230121705A1

公开(公告)日：2023-04-20

申请号：US18085228

申请日：2022-12-20

申请人： Micron Technology, Inc.

发明人： Dung V. Nguyen ,  Phone Sy Nguyen

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/30

摘要： A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

公开(公告)号：US20230118978A1

公开(公告)日：2023-04-20

申请号：US17736226

申请日：2022-05-04

申请人： SK hynix Inc.

发明人： Sung Kun PARK

IPC分类号： H01L27/11524 ,  H01L27/11519 ,  G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  H01L29/423

摘要： A semiconductor memory device may include a second conductive type first well, a second conductive type third well, a first conductive type second well, a floating gate and a selection gate. The first well may include a first active region. The third well may include a third active region. The second well may be arranged between the first well and the third well. The second well may include a second active region. The floating gate may be overlapped with the first active region, the second active region and the third active region. The selection gate may be overlapped with the second active region. The selection gate and the floating gate may be arranged side by side. A second overlap area between the second active region and the floating gate may be larger than a third overlap area between the third active region and the floating gate.

公开(公告)号：US11631465B2

公开(公告)日：2023-04-18

申请号：US17495645

申请日：2021-10-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Youn-Yeol Lee ,  Wook-Ghee Hahn

IPC分类号： G11C16/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/04 ,  G11C16/26

摘要： A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.