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    Circuit cell for a memory device or logic device
    1.
    发明授权
    Circuit cell for a memory device or logic device 有权

    公开(公告)号：US11087837B2

    公开(公告)日：2021-08-10

    申请号：US16727653

    申请日：2019-12-26

    申请人： IMEC VZW

    发明人： Trong Huynh Bao ,  Sushil Sakhare

    IPC分类号： G11C8/10 ,  G11C17/02 ,  G11C13/00 ,  G11C14/00

    摘要： A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

    Read only memory and data read method thereof
    2.
    发明授权
    Read only memory and data read method thereof 有权

    公开(公告)号：US10008279B1

    公开(公告)日：2018-06-26

    申请号：US15436453

    申请日：2017-02-17

    申请人： United Microelectronics Corp.

    发明人： Chung-Hao Cheng

    IPC分类号： G11C17/02 ,  G11C17/08

    CPC分类号： G11C17/08 ,  G11C17/10 ,  G11C2213/77

    摘要： A read only memory including a ROM cell array, a plurality of word lines and a plurality of bit lines and a word line driver. The ROM cell array has a plurality of ROM cells. Each of the ROM cells coupled to corresponding bit line and corresponding word line. The word line driver is coupled to the word lines, and respectively provides a plurality of word line signals to the word lines. Each of the ROM cells is a first type ROM cell or a second type ROM cell. The first type ROM cell includes a first top metal structure and a first bottom metal structure. The first bottom metal structure is electrically isolated from the first top metal structure. The second type ROM cell includes a second top metal structure, a second bottom metal structure, and a connection structure. The connection structure is electrically connected the second top metal structure and the second bottom metal structure.

    Field programming method for magnetic memory devices
    3.
    发明授权
    Field programming method for magnetic memory devices 有权
    磁存储器件的现场编程方法

    公开(公告)号：US09349429B2

    公开(公告)日：2016-05-24

    申请号：US14321397

    申请日：2014-07-01

    申请人： III Holdings 1, LLC

    发明人： Krishnakumar Mani

    IPC分类号： G11C11/16 ,  G11C17/02

    CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C17/02

    摘要： There is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory device; applying a first programming voltage to the selected subset of cells for a predetermined amount of time, wherein the programming voltage is selected to exceed a threshold operating voltage thereby to cause irreversible breakdown of the subset of cells; and reading selected cells of the magnetic memory device by passing a read current through a diode connected in series with each magnetic memory cell.

    摘要翻译： 提供了一种用于操作磁存储器件的方法。 该方法包括选择磁存储器件的磁存储单元的子集; 将第一编程电压施加到所选择的单元的子集达预定的时间量，其中所述编程电压被选择为超过阈值工作电压，由此导致所述单元子集的不可逆分解; 以及通过使读取电流通过与每个磁存储单元串联连接的二极管来读取所述磁存储器件的选定单元。

    NON-VOLATILE MEMORY WITH SPLIT WRITE AND READ BITLINES
    6.
    发明申请
    NON-VOLATILE MEMORY WITH SPLIT WRITE AND READ BITLINES 有权
    具有分离写入和读取位的非易失性存储器

    公开(公告)号：US20130058151A1

    公开(公告)日：2013-03-07

    申请号：US13667187

    申请日：2012-11-02

    申请人： QUALCOMM Incorporated

    发明人： Esin Terzioglu

    IPC分类号： G11C17/00 ,  G11C17/02 ,  G11C17/16

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

    摘要翻译： 非易失性存储器（NVM）位单元的读写操作具有不同的最佳参数，从而在NVM位单元的设计过程中产生冲突。 NVM位单元中的单个位线阻止了最佳的读取性能。 通过将读路径和写入路径分割在两个位线之间的NVM位单元中可以提高读取性能。 NVM位单元的读取位线具有低电容，从而提高读取操作速度并降低功耗。 NVM位单元的写位线具有低电阻以处理写操作期间存在的大电流。 NVM位单元的存储元件可以是保险丝，反熔丝，eFUSE或磁性隧道结。 差分感测读取操作可以进一步增强读取性能。

    Offset compensated sensing for magnetic random access memory
    7.
    发明授权
    Offset compensated sensing for magnetic random access memory 有权

    公开(公告)号：US07082045B2

    公开(公告)日：2006-07-25

    申请号：US11133236

    申请日：2005-05-20

    申请人： R. Jacob Baker

    发明人： R. Jacob Baker

    IPC分类号： G11C17/02

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/063

    摘要： An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.

    Electro-optical device, signal processing circuit thereof, signal processing method thereof and electronic apparatus
    8.
    发明申请
    Electro-optical device, signal processing circuit thereof, signal processing method thereof and electronic apparatus 失效
    电光装置，信号处理电路，信号处理方法及电子装置

    公开(公告)号：US20060007723A1

    公开(公告)日：2006-01-12

    申请号：US11159110

    申请日：2005-06-23

    申请人： Toru Aoki ,  Sadasumi Uchiyama

    发明人： Toru Aoki ,  Sadasumi Uchiyama

    IPC分类号： G11C17/02

    CPC分类号： G09G3/3688 ,  G09G3/2092 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0271

    摘要： An electro-optical device includes a plurality of scanning lines that extends in a row direction, a plurality of data lines that extends in a column direction, a plurality of pixels which are provided at intersections of the scanning lines and the data lines and whose gray-scale levels are designated by data signals supplied through the data lines, a common electrode that is provided so as to be opposite to pixel electrodes, a shift register that outputs sampling signals to sequentially select a plurality of blocks each composed of a plurality of the data lines, in a period where the scanning lines are selected, a sampling circuit that samples the data signals to the plurality of data lines belonging to the block selected by the sampling signal, respectively, a data signal supply circuit that changes the potential of the data signal into a higher level and a lower level than a predetermined potential in every predetermined period and then alternately outputs the potentials, and a correction circuit that superimposes, on the data signals, correction signals for correcting potential errors that are generated in the data lines belonging to each of the blocks, corresponding to the potentials of the data lines.

    摘要翻译： 电光装置包括沿行方向延伸的多条扫描线，沿列方向延伸的多条数据线，设置在扫描线和数据线的交点处的多个像素，其灰度 通过数据线提供的数据信号，与像素电极相对设置的公共电极指定的等级，移位寄存器，输出采样信号以顺序选择多个块，每个块由多个 在选择扫描线的时段中的数据线分别将数据信号分别对属于由采样信号选择的块的多个数据线进行采样的采样电路，数据信号供给电路改变 数据信号在每个预定周期内进入比预定电位更高的电平和更低的电平，然后交替地输出电位 在数据信号上叠加用于校正与数据线的电位对应的属于每个块的数据线中产生的潜在误差的校正信号。

    Offset compensated sensing for magnetic random access memory
    9.
    发明授权
    Offset compensated sensing for magnetic random access memory 失效
    磁性随机存取存储器的偏移补偿检测

    公开(公告)号：US06856532B2

    公开(公告)日：2005-02-15

    申请号：US10422850

    申请日：2003-04-25

    申请人： R. Jacob Baker

    发明人： R. Jacob Baker

    IPC分类号： G11C7/02 ,  G11C7/06 ,  G11C11/16 ,  G11C17/02

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/063

    摘要： An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.

    摘要翻译： 偏移补偿存储元件电压源，包括具有补偿电路的差分放大器，以及具有连接到差分放大器的输出的栅极的晶体管。 差分放大器的补偿电路包括补偿电容器，其在校准阶段存储补偿电压，并且在测量阶段将所存储的补偿电压施加到放大器的补偿电路的补偿输入。 来自晶体管源的反馈控制差分放大器的输出，以在测量电阻性存储元件的电阻期间在连接到源极的电阻性存储器元件两端保持标准电压，并且补偿电路提高了电压的精度 电阻性存储元件通过补偿差分放大器的偏移电压。

    Integrated circuit static write--read and erase semiconductor memory
    10.
    发明授权
    Integrated circuit static write--read and erase semiconductor memory 失效
    集成电路静态写入和擦除半导体存储器

    公开(公告)号：US5798963A

    公开(公告)日：1998-08-25

    申请号：US414383

    申请日：1995-03-31

    申请人： Adam Sempa Iga

    发明人： Adam Sempa Iga

    IPC分类号： G11C11/56 ,  G11C17/02

    CPC分类号： G11C17/02 ,  G11C11/5607 ,  G11C11/5692 ,  G11C16/24 ,  G11C7/18

    摘要： An imporved integrated circuit semiconductor static write and read and erase memory cell for storing in both one and more than one bit of binary data, having a switching transistor (M20) for switching on the memory cell, a data write bit line (26) for writing data into the cell using a column write and read and erase sense circuit (46), a data read bit line (28) for reading data stored in the memory cell, data erase bit line (32) for erasing data stored in the memory cell, a magnetic or electromagnetic element (36) for storing data in form of electromagnetism, a data reading element (34) for reading the data stored as magnetism or electromagnetism, an output current and output voltage bit line (35) for providing an output connection to a column write and read and erase sense circuit (46).

    摘要翻译： 一种用于存储在一个和多于一个位的二进制数据中的有前途的集成电路半导体静态写入和读取和擦除存储单元，具有用于接通存储器单元的开关晶体管（M20），数据写入位线（26），用于 使用列写入和读取和擦除读取电路（46）将数据写入单元，用于读取存储在存储单元中的数据的数据读取位线（28），用于擦除存储在存储器中的数据的数据擦除位线（32） 电池，用于以电磁形式存储数据的磁性或电磁元件（36），用于读取存储为磁性或电磁性的数据的数据读取元件（34），用于提供输出的输出电流和输出电压位线 连接到列写入和读取和擦除感测电路（46）。