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    Pumping capacitor and semiconductor memory device including the same
    1.
    发明授权
    Pumping capacitor and semiconductor memory device including the same 有权

    公开(公告)号：US12133372B2

    公开(公告)日：2024-10-29

    申请号：US17683562

    申请日：2022-03-01

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Yooseok Yang ,  Jongwook Park

    IPC分类号： G11C11/34 ,  G11C5/10 ,  G11C5/14 ,  H01L49/02 ,  H10B12/00

    CPC分类号： H10B12/31 ,  G11C5/10 ,  G11C5/14 ,  G11C5/145 ,  H01L28/60

    摘要： A pumping capacitor is provided. The pumping capacitor includes: first, second, third and fourth electrodes that are separately formed on a substrate; a first pumping capacitor group, wherein i first cell capacitors have lower electrodes formed on the first pad electrode and upper electrodes connected to a plate electrode, and (n−i) first cell capacitors have lower electrodes formed on the second pad electrode and upper electrodes connected to the plate electrode; and a second pumping capacitor group, wherein i second cell capacitors have lower electrodes formed on the fourth pad electrode and upper electrodes connected to the plate electrode, and (n−i) second cell capacitors have lower electrodes formed on the third pad electrode and upper electrodes connected to the plate electrode. The first pumping capacitor group and the second pumping capacitor group are connected in series, and the second pad electrode and the third pad electrode are floated.

    Non-volatile memory and voltage detecting circuit thereof
    4.
    发明授权
    Non-volatile memory and voltage detecting circuit thereof 有权

    公开(公告)号：US12094559B2

    公开(公告)日：2024-09-17

    申请号：US18072014

    申请日：2022-11-30

    申请人： eMemory Technology Inc.

    发明人： Zhe-Yi Lin

    IPC分类号： G11C5/14

    CPC分类号： G11C5/148

    摘要： A voltage detecting circuit for a non-volatile memory is provided. When a standby signal is not asserted, a power supply unit of the non-volatile memory provides an array voltage to a first node. The voltage detecting circuit includes an initial voltage generator, a capacitor, a latch and a combinational logic circuit. The initial voltage generator receives an inverted standby signal and an enable signal. An output terminal of the initial voltage generator is connected with a second node. The capacitor is coupled between the first node and the second node. An input terminal of the latch is connected with the second node. An output terminal of the latch is connected with a third node. An input terminal of the combinational logic circuit is connected with the third node. An output terminal of the combinational logic circuit generates the enable signal.

    Multiple stack high voltage circuit for memory
    5.
    发明授权
    Multiple stack high voltage circuit for memory 有权

    公开(公告)号：US12094558B2

    公开(公告)日：2024-09-17

    申请号：US18318264

    申请日：2023-05-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Perng-Fei Yuh ,  Meng-Sheng Chang ,  Tung-Cheng Chang ,  Yih Wang

    IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C17/16 ,  G11C17/18

    CPC分类号： G11C5/147 ,  G11C7/1084 ,  G11C17/165 ,  G11C17/18

    摘要： One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

    Power control circuit and control method
    6.
    发明授权
    Power control circuit and control method 有权

    公开(公告)号：US12093110B2

    公开(公告)日：2024-09-17

    申请号：US17940769

    申请日：2022-09-08

    申请人： Changxin Memory Technologies, Inc.

    发明人： Weibing Shang ,  Enpeng Gao

    IPC分类号： G06F1/324 ,  G06F1/3234 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/4074

    CPC分类号： G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/148 ,  G11C11/4074

    摘要： The present invention provides a power control circuit and control method. The power control circuit includes: a control module configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation; a power management module configured to wake up a local power supply for the memory bank according to a clock enable signal; and a power control module communicatively coupled with the power management module and configured to: send the clock enable signal to the power management module of the memory bank corresponding to the activation command in a power-saving mode; and send the clock enable signal to power management modules of the plurality of memory banks in a non-power-saving mode, where the power-saving mode indicates that a system clock is in a low-frequency state.

    System and method of power management in memory design
    8.
    发明授权
    System and method of power management in memory design 有权

    公开(公告)号：US12080372B2

    公开(公告)日：2024-09-03

    申请号：US18064048

    申请日：2022-12-09

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

    发明人： He-Zhou Wan ,  Xiuli Yang ,  Ming-En Bu ,  Mengxiang Xu ,  Zong-Liang Cao

    IPC分类号： G11C5/14

    CPC分类号： G11C5/148

    摘要： A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.