公开(公告)号：US20250072028A1

公开(公告)日：2025-02-27

申请号：US18945577

申请日：2024-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MING-TE CHEN ,  HUI-TING TSAI ,  JUN HE ,  KUO-FENG YU ,  CHUN HSIUNG TSAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

公开(公告)号：US20250070027A1

公开(公告)日：2025-02-27

申请号：US18929920

申请日：2024-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

公开(公告)号：US20250069892A1

公开(公告)日：2025-02-27

申请号：US18802472

申请日：2024-08-13

Applicant: CANON KABUSHIKI KAISHA

Inventor： KENJI YAEGASHI

IPC: H01L21/3105 ,  G03F7/00 ,  H01L21/02 ,  H01L21/67

Abstract: A planarization method of repeatedly performing a planarization process a plurality of times on the same surface of a substrate is provided. The superstrate is provided with a tapered surface connecting a side end face to a flat surface forming a lower surface facing the substrate. In a second planarization process after a first planarization process, a curable material is supplied so as to cover a region of a cured film formed under the tapered surface in the first planarization process with a liquid film formed in the second planarization process.

公开(公告)号：US20250069884A1

公开(公告)日：2025-02-27

申请号：US18238107

申请日：2023-08-25

Applicant: Applied Materials, Inc.

Inventor： Rui Lu ,  Bo Xie ,  Kent Zhao ,  Shanshan Yao ,  Xiaobo Li ,  Chi-I Lang ,  Li-Qun Xia ,  Shankar Venkataraman

IPC: H01L21/02

Abstract: Exemplary semiconductor processing methods may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursors may include Si—O bonding. The methods may include forming a plasma of the first silicon-containing precursor and the second silicon-containing precursor in the processing region. The methods may include forming a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant less than or about 3.0.

公开(公告)号：US12238924B2

公开(公告)日：2025-02-25

申请号：US17202146

申请日：2021-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kunihiro Tsubomi

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06

Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate including first and second circuit regions a first trench extending in a first direction and formed between the first and second circuit regions, wherein the first trench includes a first inner wall positioned on the first circuit region side and a second inner van positioned on the second circuit region side, and a plurality of second trenches extending in a second direction different from the first direction and firmed in the first circuit region such that the second trench communicates with the first trench at the first inner wall; and a first insulating film formed on the first and second inner walls such that the second inner wall is covered with the first insulating film without being exposed.

公开(公告)号：US12237325B2

公开(公告)日：2025-02-25

申请号：US17136860

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B41/20 ,  H10B43/20 ,  H10B53/20 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/417

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

公开(公告)号：US12237265B2

公开(公告)日：2025-02-25

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US12237214B2

公开(公告)日：2025-02-25

申请号：US18344229

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/263 ,  H01L21/31 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US12237208B2

公开(公告)日：2025-02-25

申请号：US17668452

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Ki-Jeong Kim ,  Hwan Lim ,  Hyun-Sil Hong

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H10B12/00 ,  H01L21/311

Abstract: A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

公开(公告)号：US12237167B2

公开(公告)日：2025-02-25

申请号：US17648438

申请日：2022-01-20

Applicant: Tokyo Electron Limited

Inventor： Ken Okoshi ,  Yamato Tonegawa ,  Keiji Tabuki

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/458

Abstract: With respect to a method of depositing a silicon nitride film on a surface of a substrate, the method includes depositing the silicon nitride film on the surface of the substrate by intermittently supplying trisilylamine into a processing chamber accommodating the substrate.