公开(公告)号：US20250069973A1

公开(公告)日：2025-02-27

申请号：US18236856

申请日：2023-08-22

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Zhiqiang Niu ,  Lin Lv

IPC: H01L23/31 ,  H01L21/28 ,  H01L21/304 ,  H01L23/00 ,  H01L23/498

Abstract: A chip scale semiconductor package comprises a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member. A method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.

公开(公告)号：US12237378B2

公开(公告)日：2025-02-25

申请号：US17632727

申请日：2020-08-05

Applicant: KWANSEI GAKUIN EDUCATIONAL FOUNDATION ,  TOYOTA TSUSHO CORPORATION

Inventor： Masatake Nagaya ,  Tadaaki Kaneko

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/304 ,  H01L29/16

Abstract: An object to be solved by the present invention is to provide a new technology for producing a SiC substrate in which strain is removed and capable of achieving a flat surface as flat as a surface that has been subjected to CMP. The present invention, which solves the above object, is a method for producing a SiC substrate, the method including an etching step of etching a SiC substrate having arithmetic average roughness (Ra) of a surface of equal to or less than 100 nm in an atmosphere containing Si element and C element.

公开(公告)号：US12237226B2

公开(公告)日：2025-02-25

申请号：US18447581

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Lu ,  Jun He ,  Li-Huan Chu ,  Pei-Haw Tsao

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

公开(公告)号：US20250059050A1

公开(公告)日：2025-02-20

申请号：US18722765

申请日：2021-12-23

Applicant: FUSO CHEMICAL CO., LTD.

Inventor： Chiharu Nakano ,  Fumika Kojima ,  Takahiro Tashima ,  Shuta Ozawa ,  Toshiki Chiba

IPC: C01B33/141 ,  C09K3/14 ,  H01L21/304

Abstract: A colloidal silica comprising water and silica particles, wherein the average particle size of the silica particles is 60 to 130 nm, and the content of coarse silica particles with a particle size of 0.2 μm or more among the silica particles is 10,000,000 particles/mL or less at a silica particle concentration of 1 mass.

公开(公告)号：US12230543B2

公开(公告)日：2025-02-18

申请号：US18505215

申请日：2023-11-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. Seddon

IPC: H01L21/78 ,  B23K26/00 ,  B23K26/53 ,  B23K101/40 ,  H01L21/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/683 ,  H01L23/544

Abstract: Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.

公开(公告)号：US12230541B2

公开(公告)日：2025-02-18

申请号：US17456914

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou ,  Toshiyuki Takasaki

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/3065

Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.

公开(公告)号：US20250046730A1

公开(公告)日：2025-02-06

申请号：US18781737

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz ,  Owen R. Fay ,  Cassie L. Bayless

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/3115 ,  H01L21/32 ,  H01L23/00

Abstract: Methods, apparatuses, and systems related to a semiconductor structure having an implanted alignment mark. The alignment mark may be formed by implanting a distinguishable material within a thickness of an initial semiconductor wafer and then thinning the initial semiconductor wafer. The distinguishable material may be implanted during, as a part of, or shortly following frontside processing to form active circuitry or portions thereof and then subsequently exposed through the thinning process. The resulting mark may be used to identify a relative location of circuits on the thinned wafer for subsequent processing or bonding.

公开(公告)号：US20250046657A1

公开(公告)日：2025-02-06

申请号：US18921019

申请日：2024-10-21

Applicant: ROHM CO., LTD.

Inventor： Masatoshi AKETA ,  Kazunori FUJI

IPC: H01L21/78 ,  B23K26/53 ,  H01L21/304 ,  H01L21/306 ,  H01L21/683 ,  H01L23/544

Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.

公开(公告)号：US12217966B2

公开(公告)日：2025-02-04

申请号：US17381784

申请日：2021-07-21

Applicant: DISCO CORPORATION

Inventor： Kazuma Sekiya

IPC: H01L21/304 ,  H01L21/02 ,  H01L21/78

Abstract: There is provided a processing method of a wafer. The processing method includes a protective sheet preparation step of preparing a protective sheet including a first sheet that is thermocompression-bonded to a surface of the wafer by heating, a second sheet that is laid on the first sheet and has fluidity due to the heating, and a third sheet that is laid on the second sheet and keeps flatness even with the heating. The processing method also includes a protective sheet laying step of causing a side of the first sheet to face a front surface of the wafer and executing heating to execute thermocompression bonding to lay the protective sheet on the front surface of the wafer and a grinding step of causing a side of the protective sheet to be held by a holding surface of a chuck table and grinding a back surface of the wafer.

公开(公告)号：US12198990B2

公开(公告)日：2025-01-14

申请号：US17453368

申请日：2021-11-03

Applicant: DISCO CORPORATION

Inventor： Youngsuk Kim ,  Byeongdeck Jang ,  Akihito Kawai ,  Shunsuke Teranishi

IPC: H01L21/66 ,  H01L21/304 ,  H01L21/683 ,  H01L21/78

Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole.