公开(公告)号：US20240363489A1

公开(公告)日：2024-10-31

申请号：US18754081

申请日：2024-06-25

申请人： Yibu Semiconductor Co., Ltd.

发明人： Ming Li

IPC分类号： H01L23/473 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

CPC分类号： H01L23/473 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L23/481 ,  H01L24/80 ,  H01L24/08 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1431 ,  H01L2924/1436 ,  H10B80/00

摘要： The present disclosure relates to a chip stack in the semiconductor field and a method of manufacturing the same. The chip stack comprises a plurality of stacked chips, the active surface of a first chip of the plurality of chips facing the passive surface of a second chip immediately below the first chip, and at least one open cavity embedded in the passive surface of the second chip forming a closed micro-channel with the active surface of the first chip. The microchannels in the stacked chips allow cooling micro-fluid to be introduced into the microchannels. The micro-fluid can flow from one chip to another, taking away heat generated by the chips, allowing heat dissipation of the chip stack to meet industry requirement. The micro-channels for dissipating the heat are formed while the chips are stacked. Thus, besides forming the micro-channels, no additional process steps are required to form the chip stack.

公开(公告)号：US20240363431A1

公开(公告)日：2024-10-31

申请号：US18766881

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7834 ,  H01L29/7851

摘要： A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

公开(公告)号：US20240363395A1

公开(公告)日：2024-10-31

申请号：US18231320

申请日：2023-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun-Fu KUO ,  Kuan-Da HUANG ,  Chao-Hsien HUANG ,  Li-Te LIN

IPC分类号： H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L21/76224 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/775

摘要： Embodiments of the present disclosure provide a protective layer deposited over bottom structures to protect the bottom structure during fabrication of upper structures. The protective layer may prevent STI loss and bottom spacer loss during source/drain etch back process. The protective layer may also improve process uniformity by also eliminate process loading or non-uniformity in the STI loss, fin sidewall spacer height, and recess profiles. The protective layer may also slow down fin sidewall spacer etching rate during semiconductor fin etch back, thus, improving source/drain regions profile control.

公开(公告)号：US12131912B2

公开(公告)日：2024-10-29

申请号：US18531359

申请日：2023-12-06

申请人： Intel Corporation

发明人： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/66795

摘要： Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US12131911B2

公开(公告)日：2024-10-29

申请号：US17844563

申请日：2022-06-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC分类号： H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC分类号： H01L21/30625 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66636

摘要： A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

公开(公告)号：US12122668B2

公开(公告)日：2024-10-22

申请号：US17858855

申请日：2022-07-06

申请人： Brookhaven Science Associates, LLC

发明人： Charles T. Black ,  Atikur Rahman ,  Matthew Eisaman ,  Ahsan Ashraf

IPC分类号： B81C1/00 ,  B82Y30/00 ,  B82Y40/00 ,  G02B1/118 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308 ,  H01L31/0236

CPC分类号： B81C1/00031 ,  B81C1/00111 ,  B82Y30/00 ,  G02B1/118 ,  G03F7/0002 ,  G03F7/405 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086 ,  H01L31/02363 ,  B81C2201/0132 ,  B81C2201/0149 ,  B82Y40/00 ,  H01J2237/334 ,  Y02E10/50

摘要： Methods for etching nanostructures in a substrate include depositing a patterned block copolymer on the substrate, the patterned block copolymer including first and second polymer block domains, applying a precursor to the patterned block copolymer to generate an infiltrated block copolymer, the precursor infiltrating into the first polymer block domain and generating a material in the first polymer block domain, applying a removal agent to the infiltrated block copolymer to generate a patterned material, the removal agent removing the first and second polymer block domains from the substrate, and etching the substrate, the patterned material on the substrate masking the substrate to pattern the etching. The etching may be performed under conditions to produce nanostructures in the substrate.

公开(公告)号：US20240339334A1

公开(公告)日：2024-10-10

申请号：US18747951

申请日：2024-06-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sangjine PARK ,  Seohyun KIM ,  Sukhoon KIM ,  Jihoon JEONG ,  Younghoo KIM ,  Kuntack LEE

IPC分类号： H01L21/3213 ,  G03F7/20 ,  G03F7/30 ,  G03F7/32 ,  H01L21/308 ,  H01L21/311

CPC分类号： H01L21/32139 ,  G03F7/2004 ,  G03F7/3021 ,  G03F7/325 ,  H01L21/308 ,  H01L21/31144

摘要： A substrate processing apparatus includes a processing chamber having an internal space and a substrate support within the internal space, a surface tension reducing agent supply system that supplies a surface tension reducing agent as a gas to the processing chamber, and a controller that controls the supply of the surface tension reducing agent via the surface tension reducing agent supply system. The surface tension reducing agent supply system includes at least one supply port that is configured to supply the surface tension reducing agent to the internal space and at least one discharge port that is configured to remove developer from the internal space.

公开(公告)号：US20240332419A1

公开(公告)日：2024-10-03

申请号：US18736207

申请日：2024-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Yun PENG ,  Keng-Chu LIN

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/308 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/02145 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L29/7843

摘要： A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

公开(公告)号：US20240332399A1

公开(公告)日：2024-10-03

申请号：US18732393

申请日：2024-06-03

申请人： Intel Corporation

发明人： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US12107001B2

公开(公告)日：2024-10-01

申请号：US18366274

申请日：2023-08-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry-Hak-Lay Chuang ,  Chung-Jen Huang ,  Wen-Tuo Huang ,  Wei-Cheng Wu

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L21/76229 ,  H01L21/02172 ,  H01L21/308 ,  H01L21/76283 ,  H01L21/768 ,  H01L21/76898

摘要： A semiconductor feature includes: a semiconductor substrate; a dielectric structure and a semiconductor device disposed on the semiconductor substrate; an interconnecting structure disposed in the dielectric structure and connected to the semiconductor device; an STI structure disposed in the semiconductor substrate and surrounding the semiconductor device; two DTI structures penetrating the semiconductor substrate and the STI structure and surrounding the semiconductor device; a passivation structure connected to the semiconductor substrate and the DTI structures and located opposite to the interconnecting structure; and a conductive structure surrounded by the passivation structure, penetrating the semiconductor substrate and the STI structure into the dielectric structure, located between the DTI structures and electrically connected to the semiconductor device via the interconnecting structure.