公开(公告)号：US20240363731A1

公开(公告)日：2024-10-31

申请号：US18768952

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US12131912B2

公开(公告)日：2024-10-29

申请号：US18531359

申请日：2023-12-06

申请人： Intel Corporation

发明人： Muralidhar S. Ambati ,  Ritesh Jhaveri ,  Moosung Kim

IPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/66795

摘要： Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

公开(公告)号：US12112951B2

公开(公告)日：2024-10-08

申请号：US17673905

申请日：2022-02-17

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Yixiong Yang ,  Steven C. H. Hung ,  Tianyi Huang ,  Seshadri Ganguli

IPC分类号： H01L21/28 ,  H01L21/324 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823857

摘要： Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

公开(公告)号：US20240313051A1

公开(公告)日：2024-09-19

申请号：US18674953

申请日：2024-05-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. ,  NATIONAL CHENG KUNG UNIVERSITY

发明人： TE-MING KUNG ,  YING-LANG WANG ,  KEI-WEI CHEN ,  WEN-HSI LEE ,  SHU WEI CHANG

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823412 ,  H01L29/42392

摘要： A semiconductor structure includes a substrate, a nanowire disposed over the substrate, a metal gate electrode layer and a gate dielectric layer. A dielectric layer is formed on the substrate. The nanowire has a first portion and a second portion. The nanowire has a first portion and a second portion, the first portion of the nanowire comprises a first semiconductor layer and a second semiconductor layer surrounded by the first semiconductor layer, the second portion comprises the second semiconductor layer. The metal gate electrode layer surrounds the first portion of the nanowire. The gate dielectric layer is disposed between the metal gate electrode layer and the nanowire.

公开(公告)号：US20240312789A1

公开(公告)日：2024-09-19

申请号：US18026095

申请日：2022-02-14

申请人： HITACHI HIGH-TECH CORPORATION

发明人： Takashi HATTORI ,  Masaki YAMADA ,  Keisuke AKINAGA

IPC分类号： H01L21/311 ,  H01J37/32 ,  H01L21/324

CPC分类号： H01L21/31116 ,  H01J37/32522 ,  H01J37/32816 ,  H01L21/324 ,  H01J2237/3344 ,  H01J2237/3346

摘要： A method for etching a silicon oxide film at a high selection ratio with respect to a silicon nitride film while a high etching rate of the silicon oxide film is balanced with a low etching rate of the silicon nitride film. The etching processing method is a dry etching processing method for etching a film without using plasma by supplying gas into a process chamber, the film having a side wall of a groove or a hole constituted by respective end parts of laminated film layers formed on a wafer, the laminated film layers including silicon oxide films each sandwiched between silicon nitride films, and in which the silicon oxide films are etched laterally from the end parts with the wafer being set to a low temperature equal to or less than (0.040x−42.0)° C. when a partial pressure of hydrogen fluoride gas is taken as x (Pa).

公开(公告)号：US20240304502A1

公开(公告)日：2024-09-12

申请号：US18667611

申请日：2024-05-17

申请人： Beijing E-Town Semiconductor Technology Co., Ltd. ,  Mattson Technology, Inc.

发明人： Markus Lieberer ,  Christian Pfahler ,  Markus Hagedorn ,  Michael vanAbbema ,  Alexandr Cosceev

IPC分类号： H01L21/66 ,  H01L21/324 ,  H01L21/67 ,  H01L21/687

CPC分类号： H01L22/20 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67248 ,  H01L21/68757

摘要： Preheat processes for a millisecond anneal system are provided. In one example implementation, a preheat process can include receiving a substrate on a wafer support plate in a processing chamber of a millisecond anneal system; obtaining one or more temperature measurements of the wafer support plate using a temperature sensor; and applying a preheat recipe to heat the wafer support plate based at least in part on the temperature of the wafer support plate. In one example implementation, a preheat process can include obtaining one or more temperature measurements from a temperature sensor having a field of view of a wafer support plate in a millisecond anneal system; and applying a pulsed preheat recipe to heat the wafer support plate in the millisecond anneal system based at least in part on the one or more temperature measurements.

公开(公告)号：US20240301555A1

公开(公告)日：2024-09-12

申请号：US18589845

申请日：2024-02-28

申请人： Tokyo Electron Limited

发明人： Tatsuya YAMAGUCHI

IPC分类号： C23C16/46 ,  C23C16/455 ,  C23C16/52 ,  H01L21/324 ,  H01L21/67

CPC分类号： C23C16/46 ,  C23C16/45563 ,  C23C16/52 ,  H01L21/324 ,  H01L21/67109

摘要： A substrate processing apparatus includes a processing container that accommodates a plurality of substrates in an inside thereof to perform a substrate processing on the plurality of substrates, a gas supply nozzle that supplies a gas to the inside of the processing container, and an external heater that heats the plurality of substrates from an outside of the processing container. The substrate processing apparatus further includes an internal heater that is provided independently of the gas supply nozzle in the inside of the processing container and extends at a lateral side of the plurality of substrates in a direction in which the plurality of substrates are arranged to heat the plurality of substrates.

公开(公告)号：US12087643B2

公开(公告)日：2024-09-10

申请号：US17813000

申请日：2022-07-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiu-Ko Jangjian ,  Tzu-Kai Lin ,  Chi-Cherng Jeng

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US20240282801A1

公开(公告)日：2024-08-22

申请号：US18609418

申请日：2024-03-19

申请人： SUMCO Corporation

发明人： Takeshi Kadono ,  Kazunari Kurita

IPC分类号： H01L27/146 ,  C23C14/48 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/322 ,  H01L21/324 ,  H01L29/167

CPC分类号： H01L27/14687 ,  C23C14/48 ,  C30B25/186 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/3221 ,  H01L21/324 ,  H01L27/14689 ,  H01L29/167

摘要： The present invention provides a method of producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability.
The method of producing a semiconductor epitaxial wafer includes a first step of irradiating a surface portion 10A of a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from carbon and a dopant element contained as a solid solution that are constituent elements of the cluster ions 16, in the surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer, the epitaxial layer 20 having a dopant element concentration lower than the peak concentration of the dopant element in the modifying layer 18.

公开(公告)号：US20240282586A1

公开(公告)日：2024-08-22

申请号：US18640481

申请日：2024-04-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chanyeong Jeong ,  Hoseop Choi ,  Sunggil Kang ,  Dongkyu Shin ,  Sangjin An

IPC分类号： H01L21/324 ,  H01J37/32 ,  H01L21/311 ,  H01L21/67

CPC分类号： H01L21/324 ,  H01J37/321 ,  H01J37/32229 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32724 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109

摘要： A wafer processing method includes supplying a first process gas into a wafer processing apparatus, lowering a temperature of the wafer, generating plasma using the first process gas, supplying a second process gas and mixing the second process gas with the plasma, performing a plasma process on the wafer using the plasma and the second process gas, and performing an annealing process on the wafer on which the plasma process has been performed. The lowering of the temperature of the wafer includes increasing an internal pressure of the wafer processing apparatus.