公开(公告)号：US20240362394A1

公开(公告)日：2024-10-31

申请号：US18768895

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Chan YANG ,  Ting-Wei CHIANG ,  Cheng-I HUANG ,  Hui-Zhong ZHUANG ,  Chi-Yu LU ,  Stefan RUSU

IPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/522 ,  H01L23/528 ,  H03K19/094

CPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

摘要： An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

公开(公告)号：US12080707B2

公开(公告)日：2024-09-03

申请号：US18353907

申请日：2023-07-18

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tatsuya Naito

IPC分类号： H01L29/06 ,  H01L21/76 ,  H01L21/765 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08 ,  H01L29/10 ,  H01L29/32 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L27/0635 ,  H01L21/76 ,  H01L21/765 ,  H01L27/0727 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/36 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/739 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/8613 ,  H01L29/8611

摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type drift region and a second conductivity type base region above the drift region, trench portions at an upper surface of the semiconductor substrate arrayed parallel to one another, each of them penetrating the base region, and mesa portions between respective trench portions. Among the mesa portions, at least one mesa portion includes a first conductivity type first semiconductor region having a higher concentration than the drift region, a second conductivity type second semiconductor region having a higher concentration than the base region, and a first conductivity type accumulation region between the base and drift regions and has a higher concentration than the drift region. The drift region does not extend above the accumulation region. In a longitudinal direction of the trench portions, the accumulation region extends beyond an end portion of the first semiconductor region.

公开(公告)号：US12073170B2

公开(公告)日：2024-08-27

申请号：US18354423

申请日：2023-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H03K19/094 ,  H01L23/522

CPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

摘要： An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

公开(公告)号：US12027617B2

公开(公告)日：2024-07-02

申请号：US17515645

申请日：2021-11-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akimasa Kinoshita

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/7602 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

摘要： A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p−−-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p−−-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.

公开(公告)号：US11984468B2

公开(公告)日：2024-05-14

申请号：US17793489

申请日：2021-05-28

申请人： TOWER PARTNERS SEMICONDUCTOR CO., LTD. ,  TOWER SEMICONDUCTOR LTD.

发明人： Masafumi Tsutsui

IPC分类号： H01L27/148 ,  H01L21/76 ,  H01L21/762 ,  H01L27/146 ,  H04N25/70

CPC分类号： H01L27/14818 ,  H01L21/76 ,  H01L21/762 ,  H01L27/146 ,  H01L27/1463 ,  H04N25/70

摘要： A solid-state imaging device includes a pixel array where pixels are arranged in a matrix. Each of the pixels includes a photoelectric conversion unit configured to generate a signal charge based on incident light, and an element isolation layer having light-shielding properties and surrounding a periphery of the photoelectric conversion unit. The element isolation layers of adjacent ones of the pixels in a row direction and a column direction are isolated from each other. A charge storage layer and a charge trapping layer are provided in each of regions between the element isolation layers of the adjacent ones of the pixels in the row direction and the column direction. The charge storage layer stores the signal charge. The charge trapping layer reduces incidence of light on the charge storage layer.

公开(公告)号：US11978657B2

公开(公告)日：2024-05-07

申请号：US16642132

申请日：2017-09-28

申请人： Intel Corporation

发明人： Ebony L. Mays ,  Bruce J. Tufts

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L29/0649

摘要： Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.

公开(公告)号：US11972952B2

公开(公告)日：2024-04-30

申请号：US17312594

申请日：2019-12-13

申请人： Lam Research Corporation

发明人： Ruopeng Deng ,  Xiaolan Ba ,  Tianhua Yu ,  Yu Pan ,  Juwen Gao

IPC分类号： H01L21/76 ,  H01L21/285 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC分类号： H01L21/28562 ,  H01L21/28568 ,  H01L21/76876 ,  H01L21/76877 ,  H10B41/27 ,  H10B43/27

摘要： Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.

公开(公告)号：US20240128263A1

公开(公告)日：2024-04-18

申请号：US18391678

申请日：2023-12-21

申请人： ROHM CO., LTD.

发明人： Hirotaka OTAKE

IPC分类号： H01L27/085 ,  H01L21/76 ,  H01L21/8252 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L27/085 ,  H01L21/7605 ,  H01L21/8252 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.

公开(公告)号：US11955382B2

公开(公告)日：2024-04-09

申请号：US17110818

申请日：2020-12-03

申请人： Applied Materials, Inc.

发明人： Kevin Kashefi ,  Alexander Jansen ,  Mehul Naik ,  He Ren ,  Lu Chen ,  Feng Chen

IPC分类号： H01L21/76 ,  H01L21/67 ,  H01L21/768 ,  H01L21/687

CPC分类号： H01L21/76885 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/76829 ,  H01L21/76883 ,  H01L21/68707

摘要： Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.

公开(公告)号：US20240105595A1

公开(公告)日：2024-03-28

申请号：US17934389

申请日：2022-09-22

申请人： GlobalFoundries U.S. Inc.

发明人： Johnatan A. Kantarovsky ,  Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Ephrem G. Gebreselasie

IPC分类号： H01L23/525 ,  H01L21/76 ,  H01L27/06 ,  H01L29/20

CPC分类号： H01L23/5256 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/2003

摘要： Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.