公开(公告)号：US20240363749A1

公开(公告)日：2024-10-31

申请号：US18766753

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Peng Wang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/66659 ,  H01L29/6681

摘要： The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.

公开(公告)号：US20240363731A1

公开(公告)日：2024-10-31

申请号：US18768952

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20240363590A1

公开(公告)日：2024-10-31

申请号：US18767207

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/566 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2924/1434

摘要： A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

公开(公告)号：US20240363536A1

公开(公告)日：2024-10-31

申请号：US18634187

申请日：2024-04-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jinyoung PARK ,  Heonjong SHIN ,  Jaehyun KANG ,  Youngsoo SONG

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device may include a substrate including a first active region including first active patterns spaced apart by a first interval, a second active region including second active patterns spaced apart by a second interval, first and second source/drain regions on the first and second active regions, first and second contact structures connected to the first and second source/drain regions, first and second conductive through-structures connected to the first and second contact structures, a power delivery structure in contact with bottom surfaces of the first and second conductive through-structures, a frontside interconnection structure, and a backside interconnection structure. The first conductive through-structure may be connected to the first source/drain region through the first contact structure. The second conductive through-structure may be connected to the second source/drain region through the frontside interconnection structure. The second interval may be different than the first interval.

公开(公告)号：US20240363524A1

公开(公告)日：2024-10-31

申请号：US18306267

申请日：2023-04-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Albert M. Chu ,  Reinaldo Vega ,  Ruilong Xie

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684

摘要： Embodiments of present invention provide an interconnect structure. The structure includes a metal line embedded in a dielectric layer; a first via intersecting with the metal line; and a second via intersecting with the metal line, the second via being horizontally separated from the first via by a length that is less than a blech length of the metal line, where the first and the second via extend vertically at least from a top surface of the metal line to a bottom surface of the metal line and have a width that is equal to or large than a width of the metal line. One or more method of forming the same are also provided.

公开(公告)号：US20240363490A1

公开(公告)日：2024-10-31

申请号：US18140146

申请日：2023-04-27

申请人： Intel Corporation

发明人： Mohammad Enamul KABIR ,  Keith ZAWADZKI ,  Rahim KASIM ,  Sunny CHUGH ,  Zhizheng ZHANG ,  Christopher M. PELTO ,  Babita DHAYAL ,  John Kevin TAYLOR ,  Doug INGERLY

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/58 ,  H01L29/06

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/16 ,  H01L29/0619 ,  H01L2224/16225

摘要： Through-silicon via dies are described. In an example, a semiconductor die includes a substrate having a device side and a backside. An active device layer is in or on the device side of the substrate. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the substrate. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of through silicon vias is in the substrate and extend into the dielectric structure and are connected to the plurality of metallization layers. A plurality of backside metallization structures is beneath the backside of the substrate. The plurality of through silicon vias are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.

公开(公告)号：US20240363405A1

公开(公告)日：2024-10-31

申请号：US18634671

申请日：2024-04-12

申请人： Tokyo Electron Limited

发明人： Masato SAKAMOTO ,  Tadahiro ISHIZAKA

IPC分类号： H01L21/768 ,  C23C16/02 ,  C23C16/06 ,  C23C16/52 ,  H01J37/32

CPC分类号： H01L21/76862 ,  C23C16/0227 ,  C23C16/06 ,  C23C16/52 ,  H01J37/32137 ,  H01J37/32449 ,  H01J37/32568 ,  H01L21/7685 ,  H01L21/76867 ,  H01L21/76877 ,  H01J2237/335

摘要： Provided is a substrate processing method for processing a substrate including a metal layer, the method comprising: supplying a halogen-containing gas to the substrate and reducing a metal oxide film formed on a surface of the metal layer; and supplying a reducing gas to the substrate and decreasing a residue remaining on the metal layer by supplying the halogen-containing gas.

公开(公告)号：US20240363402A1

公开(公告)日：2024-10-31

申请号：US18769054

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US20240363401A1

公开(公告)日：2024-10-31

申请号：US18201200

申请日：2023-05-24

申请人： Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Janbo Zhang ,  Li-Wei Feng

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528

摘要： A contact pad structure and a manufacturing method thereof are disclosed in the present invention. The contact pad structure includes a substrate, a first dielectric layer, a second dielectric layer, first contact pads, an etching stop layer, a first void, and a second void. The first contact pads are disposed on a first region of the substrate. The first dielectric layer is disposed on the substrate, covers the first contact pads, and includes a recess located between two adjacent first contact pads. The etching stop layer is disposed on the first dielectric layer and partially located in the recess. The second dielectric layer is disposed on the etching stop layer and partially located in the recess. The first void is disposed in the etching stop layer and located in the recess. The second void is disposed in the second dielectric layer and located in the recess.

公开(公告)号：US20240363400A1

公开(公告)日：2024-10-31

申请号：US18764971

申请日：2024-07-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Chin LEE ,  Ting-Ya LO ,  Chi-Lin TENG ,  Cherng-Shiaw TSAI ,  Shao-Kuan LEE ,  Kuang-Wei YANG ,  Gary LIU ,  Hsin-Yen HUANG ,  Hsiao-Kang CHANG ,  Shau-Lin SHUE

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L23/5329 ,  H01L23/5226 ,  H01L23/53295

摘要： A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.