公开(公告)号：US20240363759A1

公开(公告)日：2024-10-31

申请号：US18768357

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78612 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0921 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US20240363701A1

公开(公告)日：2024-10-31

申请号：US18492327

申请日：2023-10-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jongryeol Yoo

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： The present disclosure relates to semiconductor devices and their fabrication methods. One example semiconductor device comprises a substrate that includes an active region, an active pattern on the active region, a source/drain pattern on the active pattern, an active contact that extends from a top surface to a sidewall of the source/drain pattern and includes a first part that covers the sidewall of the source/drain pattern and a second part that covers the top surface of the source/drain pattern, a first layer between the source/drain pattern and the first part, and a second layer separated from the first layer and across the first part. Each of the first layer and the second layer includes a silicide layer.

公开(公告)号：US20240363690A1

公开(公告)日：2024-10-31

申请号：US18306421

申请日：2023-04-25

申请人： QUALCOMM Incorporated

发明人： Haining Yang ,  Ming-Huei Lin ,  Junjing Bao

IPC分类号： H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： Gate-all-around (GAA) field-effect transistor (FET) device employing strain material structure in inactive gate region(s) of a gate for applying channel strain to the channel(s) of the GAA FET for increased carrier mobility. The GAA FET device includes a GAA P-type (P) FET (PFET) and a GAA N-type (N) FET (NFET) served by a gate with a strain material in the inactive gate region(s) of the gate adjacent to the active gates of the GAA NFET and GAA PFET. In this manner, the strain material applies strain to both the GAA NFET and GAA PFET channels in the elongated direction of the gate in a direction orthogonal to their channel directions between the respective sources and drains, so that a strain material of the same strain type can be used to increase carrier mobility of both the GAA NFET and GAA PFET alike.

公开(公告)号：US20240363635A1

公开(公告)日：2024-10-31

申请号：US18769548

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guan-Wei Huang ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Jiun-Ming Kuo ,  Yuan-Ching Peng

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

公开(公告)号：US20240363439A1

公开(公告)日：2024-10-31

申请号：US18770861

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US20240363437A1

公开(公告)日：2024-10-31

申请号：US18770367

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shahaji B. MORE

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/02609 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

公开(公告)号：US20240363352A1

公开(公告)日：2024-10-31

申请号：US18767601

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chandrashekhar Prakash SAVANT ,  Tien-Wei YU ,  Chia-Ming TSAI

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

公开(公告)号：US12131998B2

公开(公告)日：2024-10-29

申请号：US18298172

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L23/5286 ,  H01L21/823871 ,  H01L27/092

摘要： A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.

公开(公告)号：US20240355868A1

公开(公告)日：2024-10-24

申请号：US18761077

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC分类号： H01L21/3205 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L28/24 ,  H01L21/32051 ,  H01L21/823821 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/6681 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823493 ,  H01L29/66545 ,  H01L29/7851

摘要： A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20240355707A1

公开(公告)日：2024-10-24

申请号：US18304679

申请日：2023-04-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Chin HOU ,  Li-Chun TIEN ,  Chih-LIang CHEN ,  Chi-Yu LU ,  Wei-Cheng LIN ,  Guo-Huei WU

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.