公开(公告)号：US20140103509A1

公开(公告)日：2014-04-17

申请号：US13653242

申请日：2012-10-16

申请人： STATS CHIPPAC, LTD.

发明人： Insang Yoon ,  Flynn Carson ,  Il Kwon Shim ,  SeongHun Mun

IPC分类号： H01L23/495 ,  H01L21/98 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/19

摘要： A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device.

摘要翻译： 半导体器件具有沉积在半导体管芯上方和周围的具有密封剂的半导体管芯。 通过蚀刻或LDA在密封剂的第一表面中形成开口。 可选地，在半导体管芯上形成多个凸块。 凹凸凹陷在密封剂的开口内。 导电油墨形成在开口的密封剂，凸起和侧壁的第一表面上。 导电油墨可以通过印刷方法施加。 在密封剂的与密封剂的第一表面相对的第二表面上形成互连结构。 互连结构电连接到半导体管芯。 半导体封装设置在密封剂的第一表面上，多个凸块电连接到导电油墨层。 半导体封装可以包含存储器件。

公开(公告)号：US20140097535A1

公开(公告)日：2014-04-10

申请号：US13647375

申请日：2012-10-08

申请人： QUALCOMM INCORPORATED

发明人： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L21/98 ,  H01L23/488

CPC分类号： H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

摘要： A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

摘要翻译： 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US20140049293A1

公开(公告)日：2014-02-20

申请号：US13588429

申请日：2012-08-17

申请人： Shekar Mallikarjunaswamy

发明人： Shekar Mallikarjunaswamy

IPC分类号： H03K3/353 ,  H01L21/98

CPC分类号： H01L21/8234 ,  H01L21/8221 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/66681 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

摘要： A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit

摘要翻译： 三维（3D）栅极驱动器集成电路包括堆叠在低侧集成电路上的高侧集成电路，其中高侧集成电路和低侧集成电路使用贯穿硅通孔（TSV）互连， 。 如此形成的，高侧集成电路和低侧集成电路可以形成为没有端接区域而不具有掩埋层。 3D栅极驱动器集成电路提高了高压集成的便利性，并提高了栅极驱动器集成电路的坚固性和可靠性

公开(公告)号：US20130249117A1

公开(公告)日：2013-09-26

申请号：US13426529

申请日：2012-03-21

申请人： Hun Teak Lee ,  DaeWook Yang ,  Yeongbeom Ko

发明人： Hun Teak Lee ,  DaeWook Yang ,  Yeongbeom Ko

IPC分类号： H01L23/498 ,  H01L21/98

CPC分类号： H01L21/563 ,  H01L21/6836 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/2731 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83871 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有与无效部分相对的有源侧的电路基板; 将非导电盖附接到活动侧; 形成将非导电盖和电路基板部分地切割成切口深度的分离间隙; 将背磨带附接到非导电盖; 去除所述非活性部分的一部分; 并通过去除背磨带露出非导电盖。

公开(公告)号：US20130193457A1

公开(公告)日：2013-08-01

申请号：US13609952

申请日：2012-09-11

申请人： Susumu SHIMASAKI ,  Takashi OKU ,  Junichi ISHIGURO ,  Kenichi ASAMI ,  Takashi INOUE

发明人： Susumu SHIMASAKI ,  Takashi OKU ,  Junichi ISHIGURO ,  Kenichi ASAMI ,  Takashi INOUE

IPC分类号： H01L23/49 ,  H01L21/98

CPC分类号： F21S2/005 ,  F21K9/27 ,  F21K9/90 ,  F21V19/0045 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L2224/48472

摘要： According to one embodiment, a light-emitting circuit includes: a plurality of substrates in which wiring pattern layers are formed, the substrates including light-emitting elements connected to and mounted on the wiring pattern layers; and a linear conductor having electric conductivity, the linear conductor including linear joining sections at both ends electrically connected to the wiring pattern layers of the substrates and a convex section formed to be bent in a convex shape in an intermediate section between the joining sections, and the joining sections being respectively joined to the wiring pattern layers among the plurality of substrates adjacent to one another.

摘要翻译： 根据一个实施例，发光电路包括：多个基板，其中形成布线图案层，所述基板包括连接到并安装在布线图案层上的发光元件; 以及具有导电性的直线导体，所述线状导体的两端的线状接合部电连接到所述基板的布线图案层，所述凸部形成为在所述接合部之间的中间部弯曲成凸形， 所述接合部分分别连接到彼此相邻的所述多个基板中的所述布线图案层。

公开(公告)号：US20130093067A1

公开(公告)日：2013-04-18

申请号：US13648166

申请日：2012-10-09

申请人： FLIPCHIP INTERNATIONAL, LLC

发明人： David Clark ,  Theodore G. Tessier

IPC分类号： H01L23/552 ,  H01L21/98

CPC分类号： H01L23/552 ,  H01L24/93 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/93 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2224/27

摘要： An embodiment of a method of forming an on-chip RE shield on an integrated circuit chip in accordance with the present disclosure includes providing a wafer level integrated circuit component wafer having a front side and a back side before singulation; applying a resin metal layer on a back side of the wafer; and then separating the wafer into discrete RF shielded components. It is this resin metal layer on the back side that acts effectively as the RF shield, after singulation, i.e. separation of the wafer, into discrete RF shielded components.

摘要翻译： 根据本公开的在集成电路芯片上形成片上RE屏蔽的方法的实施例包括在分割之前提供具有正面和背面的晶片级集成电​​路元件晶片; 在所述晶片的背面施加树脂金属层; 然后将晶片分成离散的RF屏蔽组件。 背面侧的这种树脂金属层在切割之后，即将晶片分离成分立的RF屏蔽部件，有效地作为RF屏蔽。

公开(公告)号：US20130027941A1

公开(公告)日：2013-01-31

申请号：US13631660

申请日：2012-09-28

申请人： Switch Bulb Company, Inc.

发明人： Glenn WHEELOCK ,  Bernhard STONAS

IPC分类号： F21V21/00 ,  H01L21/98

CPC分类号： F21V29/56 ,  A61K39/0008 ,  A61K47/6835 ,  A61K2039/507 ,  A61K2039/6056 ,  C07K14/70535 ,  C07K16/241 ,  C07K16/2887 ,  C07K2317/21 ,  C07K2317/53 ,  C07K2317/72 ,  C07K2317/92 ,  C07K2319/30 ,  F21K9/23 ,  F21V3/02 ,  F21V29/20 ,  F21V29/506 ,  F21V29/58 ,  F21V29/87 ,  F21V31/04 ,  F21Y2115/10 ,  H01L33/648 ,  Y10T29/49002

摘要： An LED bulb includes a base, a shell connected to the base, one or more LEDs, a thermally conductive liquid, and a flexible diaphragm. The one or more LEDs are disposed within the shell. The thermally conductive liquid is held within the shell. The flexible diaphragm is in fluidic connection to the thermally conductive liquid, and is configured to deflect from a first position to a second position to compensate for expansion of the thermally conductive liquid.

摘要翻译： LED灯泡包括基座，连接到基座的外壳，一个或多个LED，导热液体和柔性隔膜。 一个或多个LED设置在壳体内。 导热液体保持在壳体内。 柔性膜片与导热液体流体连接，并被构造成从第一位置偏转到第二位置以补偿导热液体的膨胀。

公开(公告)号：US20130011965A1

公开(公告)日：2013-01-10

申请号：US13618103

申请日：2012-09-14

申请人： Thomas Henry White ,  Giles V. Powell ,  Rakesh H. Patel

发明人： Thomas Henry White ,  Giles V. Powell ,  Rakesh H. Patel

IPC分类号： H01L21/98

CPC分类号： H01L23/481 ,  H01L23/5286 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.

摘要翻译： 提出了一种使用贯穿硅通孔（TSV）的分布式电源的集成电路。 集成电路具有用于提供位于顶表面的周边区域内的电源和接地的导电焊盘。 多个贯通硅通孔分布在周边区域内，并且一组TSV形成在集成电路的非外围区域内。 底表面上的导线被耦合在每个外围通孔硅通孔和相应的非外围通硅通孔之间。 功率通过周边区域内的TSV从导电焊盘分布到非外围区域内的TSV，从而向位于集成电路芯片的非周边区域内的电路供电和接地。

公开(公告)号：US20120241968A1

公开(公告)日：2012-09-27

申请号：US13071514

申请日：2011-03-25

申请人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Frederick Rodriguez Dahilig ,  Jairus Legaspi Pisigan

发明人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Frederick Rodriguez Dahilig ,  Jairus Legaspi Pisigan

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L25/105 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.

摘要翻译： 一种集成电路封装系统的制造方法，包括：形成多个镀层的柱，所述多个镀层的底部具有向内突出部，连接提升管和与所述基端相对的顶端; 定位具有面向连接提升管和向内突出部的周边端部的集成电路装置; 将接合线直接连接在向内突出部和集成电路装置上; 以及在所述集成电路器件，所述接合线，所述向内突出部和所述柱周围施加封装，所述封装暴露所述基端的一部分和所述柱的顶端。

公开(公告)号：US20120146210A1

公开(公告)日：2012-06-14

申请号：US12962806

申请日：2010-12-08

申请人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

发明人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L21/60 ,  H01L27/06

CPC分类号： H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02123 ,  H01L2224/0215 ,  H01L2224/0311 ,  H01L2224/0332 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05186 ,  H01L2224/05191 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15165 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2924/06

摘要： A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

摘要翻译： 微电子组件包括衬底和导电元件。 衬底可以具有小于10ppm /℃的CTE，具有不延伸穿过衬底的凹部的主表面和设置在凹部内的弹性模量小于10GPa的材料。 导电元件可以包括覆盖凹部并从由衬底支撑的锚定部分延伸的接合部分。 连接部分可以在主表面处至少部分地暴露以连接到微电子单元外部的部件。