公开(公告)号：US20240348164A1

公开(公告)日：2024-10-17

申请号：US18751267

申请日：2024-06-23

申请人： Marel Power Solutions, Inc.

发明人： Jean-Claude Harel

IPC分类号： H02M3/156 ,  H01L21/50 ,  H01L23/02 ,  H01L23/31 ,  H02B1/20 ,  H02K11/33 ,  H02M1/32 ,  H02M7/00 ,  H02M7/53846 ,  H05K7/14 ,  H05K7/20

CPC分类号： H02M3/1563 ,  H01L21/50 ,  H01L23/02 ,  H01L23/31 ,  H02B1/20 ,  H02K11/33 ,  H02M1/32 ,  H02M7/003 ,  H02M7/538466 ,  H05K7/1432 ,  H05K7/209 ,  H02M1/327

摘要： An apparatus may include a first device having a first metal structure, a first metal element, and a first transistor. The first metal structure may include first and second surfaces, that are flat and opposite facing. The first metal element may include first and second surfaces that are flat and opposite facing. The first transistor may include first and second terminals between which 1 amp or more of electrical current is transmitted when the first transistor is activated, wherein the first and second terminals may include first and second surfaces, respectively, that are substantially flat and opposite facing. The second surface of the first metal structure can be electrically and thermally connected to a bus bar. The first and second surfaces of the first and second terminals, respectively, may be sintered to the first and second surfaces, respectively, of the first metal structure and the first metal element, respectively.

公开(公告)号：US20240242056A1

公开(公告)日：2024-07-18

申请号：US18620657

申请日：2024-03-28

申请人： Elevation Lab, Inc.

发明人： Casey HOPKINS ,  Jacob HULL

IPC分类号： G06K19/077 ,  H01L23/02

CPC分类号： G06K19/07745 ,  H01L23/02

摘要： Mounts for securing a device to a flexible object comprise a flexible substrate configured to be operatively coupled to the flexible object and a housing coupled to the flexible substrate and having an internal void that is sized to receive the device.

公开(公告)号：US12021068B2

公开(公告)日：2024-06-25

申请号：US17492693

申请日：2021-10-04

申请人： MEDIATEK INC.

发明人： Bo-Jiun Yang ,  Wen-Sung Hsu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Kun-Ting Hung

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/105 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

摘要： A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.

公开(公告)号：US11877386B2

公开(公告)日：2024-01-16

申请号：US18154856

申请日：2023-01-16

申请人： NISSHA CO., LTD.

发明人： Yasuisa Takinishi

IPC分类号： H05K1/02 ,  H05K3/14 ,  H05K3/38 ,  H01L21/50 ,  H01L21/78 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/58 ,  H01L23/373 ,  H01L23/544 ,  H01L23/552 ,  B29C45/14 ,  H05K3/00 ,  B29L31/34

CPC分类号： H05K1/0256 ,  B29C45/14336 ,  H05K3/0014 ,  H05K3/0091 ,  H05K3/0094 ,  B29L2031/3425

摘要： An injection molded article is provided with: a flat molded resin body that has a flat rectangular parallelepiped shape and is formed from an injection molded resin; and a base sheet affixed to the surface of the molded resin body. The base sheet has formed therein a first conductive layer on a first surface and a through hole passing through from the first surface to a second surface. The through hole is filled with a conductive material, and a second conductive layer is formed so as to be electrically connected with the first conductive layer via the conductive material with which the through hole is filled. In addition, a sealing material is formed on the first conductive layer so as to cover the through hole. The molded resin body is fixed together with the first surface side of the base sheet so as to cover the sealing material.

公开(公告)号：US11854988B2

公开(公告)日：2023-12-26

申请号：US17107181

申请日：2020-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien-Hsun Lee

IPC分类号： H01L23/02 ,  H01L23/538 ,  H01L23/31 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/5389 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379

摘要： A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

公开(公告)号：US11842986B1

公开(公告)日：2023-12-12

申请号：US17973905

申请日：2022-10-26

申请人： Eliyan Corporation

发明人： Farjadrad Ramin

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/31 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/151 ,  H01L2924/181

摘要： Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and a first integrated circuit (IC) chip disposed on the package substrate. The first IC chip includes first core circuitry, and first interface circuitry for communicating with the first core circuitry. A second IC chip is disposed on the package substrate and includes second core circuitry and second interface circuitry for communicating with the second core circuitry. The second interface circuitry exhibits a non-matching interface with respect to the first interface circuitry. Interface adapter circuitry couples to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.

公开(公告)号：US11837578B2

公开(公告)日：2023-12-05

申请号：US17674854

申请日：2022-02-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC分类号： H01L27/10 ,  H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L25/0655 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/17 ,  H01L24/30 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373

摘要： A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

公开(公告)号：US11798932B2

公开(公告)日：2023-10-24

申请号：US17855664

申请日：2022-06-30

申请人： Intel Corporation

发明人： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/488 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L23/00 ,  H05K1/11 ,  H05K3/40 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US11791269B2

公开(公告)日：2023-10-17

申请号：US16931690

申请日：2020-07-17

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manepalli

IPC分类号： H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K7/00 ,  H05K7/02 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/52 ,  H01L21/56 ,  H01L21/60 ,  H01L21/84 ,  H01L21/768 ,  H01L23/00 ,  H01L23/02 ,  H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/15 ,  H01L23/18 ,  H01L23/29 ,  H01L23/31 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L23/5383 ,  H01L24/13 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/1579 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

摘要： Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US11791228B2

公开(公告)日：2023-10-17

申请号：US16380486

申请日：2019-04-10

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Kristof Darmawikarta ,  Roy Dittler ,  Jeremy Ecton ,  Darko Grujicic

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/488

CPC分类号： H01L23/3114 ,  H01L23/3128 ,  H01L23/488

摘要： Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.