公开(公告)号：US11635777B2

公开(公告)日：2023-04-25

申请号：US16427289

申请日：2019-05-30

申请人： PHISON ELECTRONICS CORP.

发明人： Jia-Huei Yeh ,  Chao-Ta Huang ,  Yi-Feng Li ,  Po-Chieh Chiu ,  Chun-Yu Ling

IPC分类号： G05D23/24 ,  G05D23/19 ,  G01R31/28 ,  H01L23/34

摘要： A temperature control circuit for an electronic device is provided. The temperature control circuit includes a temperature detector, a status detection circuit and a control circuit. The temperature detector is configured to detect a temperature of the electronic device and generate first evaluation information. The status detection circuit is configured to detect a work status of at least one circuit module in the electronic device and generate second evaluation information. The control circuit is configured to adjust at least one electronic parameter of the electronic device according to the first evaluation parameter and the second evaluation parameter to control the temperature of the electronic device.

公开(公告)号：US11632856B2

公开(公告)日：2023-04-18

申请号：US17366836

申请日：2021-07-02

申请人： RAYTHEON COMPANY

发明人： Andrew Southworth ,  Kevin Wilder ,  James Benedict ,  Mary K. Herndon ,  Thomas V. Sikina ,  John P. Haven

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/26 ,  H05K3/30 ,  H05K5/00 ,  H05K5/06 ,  H05K9/00 ,  H01L23/34 ,  H01L23/498 ,  H01L23/552 ,  H01Q1/38 ,  H01Q1/52 ,  H05K3/00

摘要： A circuit assembly is provided and includes a printed circuit board (PCB) having a circuit element region and defining a trench surrounding an entirety of the circuit element region, a circuit element disposed within the circuit element region of the PCB; and a Faraday wall. The Faraday wall includes a solid, unitary body having a same shape as the trench. The Faraday wall is disposed within the trench to surround an entirety of the circuit element.

公开(公告)号：US11621237B2

公开(公告)日：2023-04-04

申请号：US16247312

申请日：2019-01-14

申请人： Intel Corporation

发明人： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh ,  Mohanraj Prabhugoud ,  Chong Zhao

IPC分类号： H05K1/02 ,  H01L23/66 ,  H01L23/498 ,  H01L23/34 ,  H01B7/04 ,  G02B6/42 ,  H01B3/30 ,  H01B7/08 ,  H01L25/10 ,  H05K1/18

摘要： Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

公开(公告)号：US20230087724A1

公开(公告)日：2023-03-23

申请号：US17994053

申请日：2022-11-25

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Boning Huang ,  Wentao Yang ,  Junhe Wang

IPC分类号： H01L23/34 ,  H01L29/739 ,  H01L27/06 ,  H01L23/552 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

摘要： The technology of this disclosure relates to an IGBT chip integrating a temperature sensor, and relates to the field of power device technologies, to improve accuracy of temperature monitoring of the IGBT chip. The IGBT chip integrating the temperature sensor includes a cell region, an emitter pad, a gate pad, a gate finger structure, a temperature sensing module, and a conductive shielding structure. The emitter pad is electrically connected to emitters of a plurality of IGBT cells. The gate finger structure is connected between the gate pad and gates of the plurality of IGBT cells. The temperature sensing module includes a temperature sensor, an anode pad, a cathode pad, and a metal lead. The temperature sensor and at least a part of the metal lead are located in the gate finger structure and are insulated from the gate finger structure.

公开(公告)号：US20230079915A1

公开(公告)日：2023-03-16

申请号：US17944077

申请日：2022-09-13

申请人： NICHIA CORPORATION

发明人： Takuya HASHIMOTO

IPC分类号： H01L25/075 ,  H01L23/34 ,  H01L33/48 ,  H01L33/62

摘要： A light-emitting device includes a mounting member, first to third light-emitting elements mounted on a mounting surface, and first to third protective elements mounted on the mounting surface and respectively electrically connected to the first to third light-emitting elements. In a plan view viewed along a normal direction of the mounting surface, at least a part of the first protective element is disposed between the first light-emitting element and the second light-emitting element, at least a part of the second protective element and at least a part of the third protective element are disposed between the second light-emitting element and the third light-emitting element, and the second light-emitting element is disposed between the first light-emitting element and the third light-emitting element.

公开(公告)号：US11605609B2

公开(公告)日：2023-03-14

申请号：US16788428

申请日：2020-02-12

申请人： General Electric Company

发明人： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC分类号： H01L23/00 ,  H01L23/34 ,  H01L23/538 ,  H05K3/30 ,  H05K3/46 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/10 ,  H01L23/42 ,  H01L23/433 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36

摘要： A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US11594520B2

公开(公告)日：2023-02-28

申请号：US17073953

申请日：2020-10-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC分类号： H01L23/34 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

摘要： A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US11594469B2

公开(公告)日：2023-02-28

申请号：US17228018

申请日：2021-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chang Ku ,  Hung-Chi Li ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC分类号： H01L23/34 ,  H01L23/427 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

摘要： A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

公开(公告)号：US20230052394A1

公开(公告)日：2023-02-16

申请号：US17973926

申请日：2022-10-26

申请人： Mavagail Technology, LLC

发明人： Darryl G. Walker

IPC分类号： H03K17/14 ,  G01K7/01 ,  G01K1/14 ,  G05F3/26 ,  G06F1/08 ,  G11C11/406 ,  G11C11/419 ,  H01L23/34 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G01K3/00

摘要： An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

公开(公告)号：US11553599B2

公开(公告)日：2023-01-10

申请号：US16713527

申请日：2019-12-13

申请人： AT&S (Chongqing) Company Limited

发明人： Yu-Hui Wu

IPC分类号： H05K1/09 ,  H05K1/11 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/36 ,  H05K3/40 ,  H01L21/02 ,  H01L21/28 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L21/78 ,  H01L21/98 ,  H01L21/768 ,  H01L23/00 ,  H01L23/06 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L23/36 ,  H01L23/50 ,  H01L23/52 ,  H01L23/488 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H05K3/46 ,  H05K1/14

摘要： A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.