公开(公告)号：US20240363478A1

公开(公告)日：2024-10-31

申请号：US18141118

申请日：2023-04-28

申请人： Littelfuse, Inc.

发明人： Aalok Bhatt ,  FRANCOIS PERRAUD ,  CYNTHIA SELKE ,  RHODRI HUGHES ,  TIBURCIO MALDO

IPC分类号： H01L23/373 ,  H01L23/31

CPC分类号： H01L23/3735 ,  H01L23/3107

摘要： A substrate package arrangement may include a substrate that contains a ceramic body, a top metal layer, disposed on a top side of the ceramic body, and a bottom metal layer, disposed on a bottom side of the ceramic body, opposite the top surface. The substrate package arrangement may further include a lead structure, electrically connected to the top metal layer, and being electrically isolated from the bottom metal layer, wherein the substrate and lead structure are arranged in a discrete package, and wherein the ceramic body is formed of a high thermal conductivity material.

公开(公告)号：US20240363477A1

公开(公告)日：2024-10-31

申请号：US18028850

申请日：2022-08-26

申请人： Honor Device Co., Ltd.

发明人： Erliang Li ,  Hanghang Dong ,  Junjie Yang

IPC分类号： H01L23/373 ,  G06F1/16 ,  H01L23/367 ,  H05K7/20

CPC分类号： H01L23/3735 ,  H01L23/3675 ,  H01L23/3736 ,  H05K7/20409 ,  G06F1/1613

摘要： This application discloses a thermal pad, a heat dissipation module, and an electronic device, and relates to the field of thermal pad technologies. The thermal pad includes a pad body. The pad body is provided with a hollowed-out part, and the hollowed-out part is filled with a liquid metal material layer. This application may be applied to electronic devices such as notebook computers.

公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC分类号： H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

摘要： A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US20240355724A1

公开(公告)日：2024-10-24

申请号：US18683431

申请日：2021-10-25

申请人： Mitsubishi Electric Corporation

发明人： Tatsuya KAWASE

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/15 ,  H01L23/373 ,  H01L25/18

CPC分类号： H01L23/49838 ,  H01L23/15 ,  H01L23/373 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/29 ,  H01L24/30 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/29111 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48153 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device includes a first insulating material, a first conductor pattern provided on an upper surface of the first insulating material, a second conductor pattern provided on a lower surface of the first insulating material, a semiconductor element bonded to an upper surface of the first conductor pattern by a first bonding material, and a first base plate bonded to a lower surface of the second conductor pattern by a second bonding material, in which a ratio κ1/D1 satisfies κ1/D1≤35×104W/(m2K) where κ1 represents thermal conductivity of the first insulating material and D1 represents a thickness of the first insulating material, solidus temperature of the first bonding material is equal to or higher than solidus temperature of the second bonding material, and a difference between the solidus temperature of the first bonding material and the solidus temperature of the second bonding material is within 40° C.

公开(公告)号：US12125794B2

公开(公告)日：2024-10-22

申请号：US18167879

申请日：2023-02-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/373 ,  H01L25/065

CPC分类号： H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/3736 ,  H01L23/5386 ,  H01L25/0657

摘要： A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US12125766B2

公开(公告)日：2024-10-22

申请号：US17537689

申请日：2021-11-30

申请人： Samsung Electronics Co., Ltd.

发明人： Tae Hwan Kim ,  Jae Choon Kim ,  Kyung Suk Oh

IPC分类号： H01L35/32 ,  F25B21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/38 ,  H01L23/48 ,  H01L23/522 ,  H01L25/16

CPC分类号： H01L23/38 ,  H01L23/3121 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/16 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/73204

摘要： A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.

公开(公告)号：US12125739B2

公开(公告)日：2024-10-22

申请号：US18151235

申请日：2023-01-06

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Michael Carroll

IPC分类号： H01L21/762 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373 ,  H01L23/66

CPC分类号： H01L21/76245 ,  H01L21/565 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/66 ,  H01L24/17

摘要： The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

公开(公告)号：US20240347497A1

公开(公告)日：2024-10-17

申请号：US18301367

申请日：2023-04-17

申请人： International Business Machines Corporation

发明人： SHIDONG LI ,  Kenneth Charles Marston ,  Kalind BARAYA

IPC分类号： H01L23/00 ,  H01L23/373 ,  H01L23/473

CPC分类号： H01L24/32 ,  H01L23/3733 ,  H01L23/473 ,  H01L24/29 ,  H01L24/83 ,  H01L23/3738 ,  H01L23/481 ,  H01L2224/29109 ,  H01L2224/29147 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32235 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2924/0544

摘要： Semiconductor structures are provided with five different cooling elements directly bonded to a semiconductor chip. The cooling element is directly bonded to the backside of a thinned semiconductor substrate or to the front side back-end-of-line (BEOL) interconnect wiring of the semiconductor chip. The cooling element replaces a carrier wafer on semiconductor chips with backside BEOL interconnect wiring. Each of the five cooling elements provide better thermal conductivity for the semiconductor structure when directly bonded to the front side BEOL interconnect wiring than the carrier wafer typically bonded to a semiconductor chip with backside BEOL interconnect wiring. The cooling element is one of a copper cooling element with water-filled microchannels, or a copper plate, a silicon cooling element with water-filled microchannels, a silicon carbide plate, or a glass plate with copper-filled vias. The cooling element is directly bonded to the semiconductor chip by a hybrid bond.

公开(公告)号：US20240347417A1

公开(公告)日：2024-10-17

申请号：US18634630

申请日：2024-04-12

申请人： Robert Bosch GmbH

发明人： Andreas Burghardt

IPC分类号： H01L23/373 ,  H01L21/48

CPC分类号： H01L23/3735 ,  H01L21/4857

摘要： A device including a ceramic substrate having a first side and an opposite second side. A first brazing layer is arranged on the first side in regions and a first copper layer is arranged on the first brazing layer. A second brazing layer is arranged on the second side and a second copper layer is arranged on the second brazing layer. The first copper layer has first trenches which extend from a surface of the first copper layer to the first side. The second copper layer has second trenches which extend from a surface of the second copper layer to at least one surface of the second brazing layer. The second copper layer can be conductively connected to a heat sink. The first trenches have first trench bottoms and the second trenches have second trench bottoms, wherein the first trench bottoms are wider than the second trench bottoms.

公开(公告)号：US20240339376A1

公开(公告)日：2024-10-10

申请号：US18403864

申请日：2024-01-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seunghyun CHO ,  Eunho CHO

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/373 ,  H01L21/481 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A chip on film package includes a flexible base film having a first surface and a second surface opposite to the first surface, the base film having a chip mounting region on the first surface; a plurality of wirings extending from the chip mounting region on the first surface of the base film in a first direction parallel to an extending direction of the base film; a semiconductor chip mounted on the chip mounting region on the first surface of the base film and electrically connected to the plurality of wirings; a heat dissipation layer provided to have a predetermined thickness in a depth direction from the second surface of the base film in an area overlapping the chip mounting region, the heat dissipation layer including a laser-induced carbon material; and an insulating layer covering the heat dissipation layer on the second surface of the base film.