公开(公告)号：US20250031434A1

公开(公告)日：2025-01-23

申请号：US18353389

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Jih-Churng Twu ,  Su-Chun Yang ,  Shih-Peng Tai ,  Yu-Hao Kuo

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

公开(公告)号：US20250029936A1

公开(公告)日：2025-01-23

申请号：US18672372

申请日：2024-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a substrate that includes a first surface and a second surface that is opposite to the first surface, where the first surface includes a first region and a second region, where the substrate includes a wiring circuit layer; first connection pads in the first region of the substrate and second connection pads in the second region of the substrate, a semiconductor chip structure that is on the first region of the substrate and is connected to the first connection pads by conductive bumps, a stiffener that extends along the first side and is in the first region of the substrate, an underfill on the first region of the substrate, where the underfill is spaced apart from the stiffener, and external connection conductors that are on the second surface of the substrate and electrically connected to the wiring circuit layer.

公开(公告)号：US20250029927A1

公开(公告)日：2025-01-23

申请号：US18419266

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGBAE KIM

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, a first device on the package substrate and a second device on the package substrate and horizontally spaced apart from the first device, where the package substrate includes a first redistribution layer, a second redistribution layer on the first redistribution layer, a core section between the first redistribution layer and the second redistribution layer, a dummy structure in the first redistribution layer and on a bottom surface of the core section and a bridge chip in the second redistribution layer and on a top surface of the core section, and where a thermal conductance of the dummy structure is greater than a thermal conductance of the first redistribution layer.

公开(公告)号：US20250029914A1

公开(公告)日：2025-01-23

申请号：US18430241

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Kwang-Soo KIM ,  Jinchan AHN

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. Each of the logic die and the interposer die has a first width.

公开(公告)号：US20250029913A1

公开(公告)日：2025-01-23

申请号：US18419084

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesic LEE ,  Youngbae Kim

IPC: H01L23/498 ,  H01L21/027 ,  H01L23/00

Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor layer, and a first connection pad and a first insulation layer that are provided on a surface of the first semiconductor layer extending in a first direction; and a second semiconductor chip including a second semiconductor layer, and a second connection pad and a second insulation layer that are provided on a surface of the second semiconductor layer. The first connection pad directly contacts the second connection pad and is provided on the second connection pad in a second direction that is perpendicular to the first direction. The first insulation layer directly contacts the second insulation layer, the first insulation layer is provided on the second insulation layer in the second direction. A width of the second connection pad in the first direction is smaller than a width of the first connection pad in the first direction.

公开(公告)号：US20250029910A1

公开(公告)日：2025-01-23

申请号：US18909897

申请日：2024-10-08

Applicant: Innolux Corporation

Inventor： Yeong-E Chen ,  Yi-Hung Lin ,  Cheng-En Cheng ,  Wen-Hsiang Liao ,  Cheng-Chi Wang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: An electronic component includes a first electronic unit including a plurality of pads, a first conductive layer, a second conductive layer, a first insulating layer having a first thickness, a second insulating layer having a second thickness, a second electronic unit, and a solder ball. The first conductive layer is disposed between the first electronic unit and the second conductive layer, and electrically connected to at least one of the pads through a conductive via. The first insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed between the first insulating layer and the second insulating layer. The first thickness is different from the second thickness. The second conductive layer is disposed between the first conductive layer and the second electronic unit. The second conductive layer is electrically connected to the second electronic unit through the solder ball.

公开(公告)号：US12205939B2

公开(公告)日：2025-01-21

申请号：US17501108

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohwan Lee ,  Seokhyun Lee ,  Jeongho Lee

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.

公开(公告)号：US12205935B2

公开(公告)日：2025-01-21

申请号：US17298164

申请日：2019-09-12

Applicant: AISIN CORPORATION

Inventor： Takanobu Naruse

IPC: H01L25/16 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H05K1/02 ,  H05K1/18

Abstract: The present invention supplies electric power to a semiconductor module appropriately and also curbs the number of wiring layers of a main substrate on which the semiconductor module is mounted. A semiconductor device (10) is provided with a main substrate (90) and a semiconductor module (1). A first power supply circuit (71), the semiconductor module (1), and a first element (9) are mounted on the main substrate (90). The semiconductor module (1) is provided with a second element (2, 3) and a module substrate (4) on which the second element (2, 3) is mounted. The first power supply circuit (71) supplies electric power (Vcc) to the first element (9). The semiconductor module (1) is further provided with a second power supply circuit (72) mounted on the module substrate (4), and the second power supply circuit (72) supplies electric power (Vcc) to the second element (2, 3).

公开(公告)号：US12205916B2

公开(公告)日：2025-01-21

申请号：US18436643

申请日：2024-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shenggao Li

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes forming a first package component, and forming a first plurality of electrical connectors at a first surface of the first package component. The first plurality of electrical connectors are laid out as having a honeycomb pattern. A second package component is bonded to the first package component, wherein a second plurality of electrical connectors at a second surface of the second package component are bonded to the first plurality of electrical connectors.

公开(公告)号：US20250022866A1

公开(公告)日：2025-01-16

申请号：US18409931

申请日：2024-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyeon JEONG ,  Hyunki KIM ,  Junga LEE

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate, a passive element on the substrate, and a connection terminal connecting the substrate to the passive element. The substrate includes a base portion comprising an element pad connected to the connection terminal, and an upper insulating layer on the base portion to expose at least a portion of the base portion. The passive element is in contact with the upper insulating layer, and a thickness of the connection terminal and a thickness of the upper insulating layer are equal to each other.