公开(公告)号：US20250072017A1

公开(公告)日：2025-02-27

申请号：US18455665

申请日：2023-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Atsushi Ogino ,  Baozhen Li ,  Dureseti Chidambarrao ,  Matthew Stephen Angyal

IPC: H01G4/06 ,  H01L23/522

Abstract: A MIM capacitor including a bottom metal layer on a substrate, a first contact window in the bottom metal layer; and a first dielectric spacer disposed within the first contact window on vertical sidewalls of the bottom metal layer, where the first dielectric spacer has a rounded upper surface, where a bottom most surface of the bottom metal layer is substantially flush with a bottom most surface of the first insulator layer. A method including forming a bottom metal layer on a substrate, forming a first contact window in the bottom metal layer, and forming a first dielectric spacer disposed within the first contact window on vertical sidewalls of the bottom metal layer, wherein the first dielectric spacer has a rounded upper surface.

公开(公告)号：US20250071998A1

公开(公告)日：2025-02-27

申请号：US18452737

申请日：2023-08-21

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.,

Inventor： Masanori TSUTSUMI ,  Hiroyuki TANAKA ,  Ryota SUZUKI ,  Tomoyuki OBU

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes source-level material layers containing a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and into an upper portion of the source-level material layers, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. The source contact layer includes a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion, having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel, and contacting a bottommost insulating layer within the alternating stack.

公开(公告)号：US20250071996A1

公开(公告)日：2025-02-27

申请号：US18944590

申请日：2024-11-12

Applicant: Lodestar Licensing Group, LLC

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  G11C16/04 ,  H01L21/02 ,  H01L21/67 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B51/20

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20250070056A1

公开(公告)日：2025-02-27

申请号：US18945109

申请日：2024-11-12

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20250069990A1

公开(公告)日：2025-02-27

申请号：US18403146

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Hsin Shih ,  Kuan-Hsun Wang ,  Chih Hsin Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58

Abstract: An embodiment includes a device, the device including a first die including a first surface and a second surface opposite the first surface. The first die includes a plurality of through substrate vias (TSVs) exposed from the second surface of the first die. The device also includes a guard ring surrounding the plurality of TSVs. The device also includes a dummy metallization pattern surrounding the guard ring. The device also includes an active metallization pattern connected to active devices in the first die.

公开(公告)号：US20250069950A1

公开(公告)日：2025-02-27

申请号：US18948269

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Paolo Tessariol

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, first dielectric-filled trenches extending vertically through the stack structure, and at least one second dielectric-filled trench intersecting the first dielectric-filled trenches. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The first dielectric-filled trenches divide the stack structure into blocks and extend horizontally in a first direction. At least one second dielectric-filled trench extends horizontally in a second direction orthogonal to the first direction. At least one second dielectric-filled trench has boundaries defined by at least one staircase structure having steps defined by horizontal ends of the tiers in the first direction. Memory devices and electronic systems are also described.

公开(公告)号：US12237342B2

公开(公告)日：2025-02-25

申请号：US18509459

申请日：2023-11-15

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Masayoshi Fuchi

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

公开(公告)号：US12237326B2

公开(公告)日：2025-02-25

申请号：US17676852

申请日：2022-02-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang

IPC: H01L27/08 ,  H01L23/522 ,  H01L49/02

Abstract: A finger-type semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral power supply strips. The second conductive structure includes longitudinal second conductive strips and P lateral power supply strip(s). The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit (IC) layer; and the longitudinal first conductive strips include a first row of strips and a second row of strips. The lateral power supply strips are located in a second IC layer, and coupled to the first and second rows of strips through vias. The P lateral power supply strip(s) is/are located in the second IC layer, and include(s) a first-capacitor-group power supply strip that is coupled to K strip(s) of the longitudinal second conductive strips through K via(s). The P and K are positive integers.

公开(公告)号：US12237268B2

公开(公告)日：2025-02-25

申请号：US18660550

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US12237260B2

公开(公告)日：2025-02-25

申请号：US17541587

申请日：2021-12-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Hsien Chou

IPC: H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. A top surface of the first conductive plug is greater than a bottom surface of the first conductive plug. The semiconductor device structure further includes a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug.