公开(公告)号：US20240363791A1

公开(公告)日：2024-10-31

申请号：US18766336

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC分类号： H01L31/18 ,  H01L23/544 ,  H01L27/146

CPC分类号： H01L31/1876 ,  H01L23/544 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/186 ,  H01L31/1888 ,  H01L2223/54426

摘要： A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US20240363526A1

公开(公告)日：2024-10-31

申请号：US18421431

申请日：2024-01-24

申请人： Samsung Electronics Co., Ltd.

发明人： Kyuhoon CHOI ,  Seungseok HA ,  Seowoo NAM

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H10B12/00 ,  H10B41/30 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L23/544 ,  H10B12/09 ,  H10B12/50 ,  H10B41/30 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  H01L2223/54426

摘要： A semiconductor device according to some example embodiments may include: a substrate having a first region and a second region; a lower interlayer insulating layer on the first region and the second region of the substrate; an upper interlayer insulating layer on the lower interlayer insulating layer; a via structure penetrating through the upper interlayer insulating layer in the first region; a plurality of metal wirings extending in a first direction on the via structure and electrically connected to the via structure; trenches on a same level as that of the via structure and in the upper interlayer insulating layer, in the second region; and a dummy wiring layer having a curved structure along upper surfaces of the trenches, the upper interlayer insulating layer, and the lower interlayer insulating layer.

公开(公告)号：US20240355757A1

公开(公告)日：2024-10-24

申请号：US18408215

申请日：2024-01-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonghyun Kim ,  Sangjin Kim ,  Jaesuk Park ,  Yigwon Kim ,  Changmin Park ,  Hyungju Ryu

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54426

摘要： The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including a logic cell region and a key region, a dummy active pattern on the key region, and a key pattern in the dummy active pattern. The key pattern includes a key cell that is recessed at an upper portion of the substrate. The key cell includes a bottom surface lower than a top surface of the dummy active pattern, and a plurality of inner lateral surfaces that surround the bottom surface. The inner lateral surfaces include a first inner lateral surface and a second inner lateral surface opposite to the first inner lateral surface. A ratio of a silicon atom surface density of the second inner lateral surface to a silicon atom surface density of the first inner lateral surface is in a range of about 0.9 to about 1.1.

公开(公告)号：US12119307B2

公开(公告)日：2024-10-15

申请号：US17504125

申请日：2021-10-18

申请人： ROCKLEY PHOTONICS LIMITED

发明人： Chia-Te Chou ,  Brett Sawyer ,  David McCann

IPC分类号： H01L23/544 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2224/1301 ,  H01L2224/16167 ,  H01L2224/17517 ,  H01L2924/146 ,  H01L2924/15323

摘要： An assembly. In some embodiments, the assembly includes a first semiconductor chip, a substrate, and a first alignment element. The alignment of the first semiconductor chip and the substrate may be determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip.

公开(公告)号：US20240332206A1

公开(公告)日：2024-10-03

申请号：US18739424

申请日：2024-06-11

申请人： NXP USA, INC.

发明人： Michael B. Vincent ,  Scott M. Hayes ,  Antonius Hendrikus Jozef Kamphuis

IPC分类号： H01L23/544 ,  H01L21/48 ,  H01L23/498 ,  H01Q1/22

CPC分类号： H01L23/544 ,  H01L21/4853 ,  H01L23/49838 ,  H01Q1/2283 ,  H01L2223/54426

摘要： A method of forming a self-aligned waveguide is provided. The method includes forming a first alignment feature on a packaged semiconductor device and a second alignment feature on a waveguide structure. A solder material is applied to the first alignment feature or the second alignment feature. The waveguide structure is placed onto the packaged semiconductor device such that the second alignment feature overlaps the first alignment feature. The solder material is reflowed to cause the waveguide structure to align with the packaged semiconductor device.

公开(公告)号：US12107008B2

公开(公告)日：2024-10-01

申请号：US17523086

申请日：2021-11-10

申请人： International Business Machines Corporation

发明人： Soon-Cheon Seo ,  Dexin Kong ,  Muthumanickam Sankarapandian ,  Raghuveer Reddy Patlolla

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/544

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L23/544 ,  H01L2223/54426

摘要： A method of manufacturing a semiconducting device that includes forming first opening for forming bottom electrode hole in a first area of a semiconductor wafer; forming a deeper second opening for overlay/alignment hole in second area; depositing a bottom electrode metal layer filling the first opening to form a bottom electrode and partially filling the second opening. A layer of sacrificial material is then deposited above the bottom electrode layer and completely filling the second opening. A chemical-mechanical planarization process is performed to remove the -bottom electrode metal and -sacrificial layer, the -sacrificial material layer being removed above a surface defined atop the filled remaining portion above the second opening. The sacrificial layer material is removed in the remaining portion of the second opening. The second opening providing an overlay/alignment feature topography detectable for alignment by lithography and for overlay measurement on the overlay metrology tool.

公开(公告)号：US12106962B2

公开(公告)日：2024-10-01

申请号：US17341183

申请日：2021-06-07

申请人： United Microelectronics Corp.

发明人： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

IPC分类号： H01L21/033 ,  G03F7/00 ,  G03F7/20 ,  H01L21/311 ,  H01L21/66 ,  H01L23/544

CPC分类号： H01L21/0337 ,  G03F7/2022 ,  G03F7/70633 ,  H01L21/31144 ,  H01L22/20 ,  H01L23/544

摘要： The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

公开(公告)号：US20240321767A1

公开(公告)日：2024-09-26

申请号：US18736947

申请日：2024-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Hao Yeh ,  Kuan-Jung Chen ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Hung-Lin Chen

IPC分类号： H01L23/544 ,  G03F9/00

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  H01L2223/54426 ,  H01L2223/5446

摘要： The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.

公开(公告)号：US12096706B2

公开(公告)日：2024-09-17

申请号：US18232750

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huei-Tsz Wang ,  Po-Shu Wang ,  Wei-Ming Wang

IPC分类号： H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/85 ,  H10N70/20 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H10N50/80

CPC分类号： H10N70/841 ,  H10B61/22 ,  H10B63/30 ,  H10N50/85 ,  H10N70/011 ,  H10N70/063 ,  H10N70/20 ,  H10N70/24 ,  H10N70/245 ,  H10N70/826 ,  H10N70/881 ,  H10N70/8825 ,  H10N70/8833 ,  H10N70/8836 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/544 ,  H01L2223/54426 ,  H10B63/80 ,  H10B63/84 ,  H10N50/80 ,  H10N70/021

摘要： A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

公开(公告)号：US20240304651A1

公开(公告)日：2024-09-12

申请号：US18295354

申请日：2023-04-04

申请人： CANON KABUSHIKI KAISHA

发明人： TAKASHI IKEDA

IPC分类号： H01L27/146 ,  G01N23/046 ,  G01N23/083 ,  G01T1/24 ,  H01L23/544

CPC分类号： H01L27/14661 ,  G01N23/046 ,  G01N23/083 ,  G01T1/247 ,  H01L23/544 ,  H01L27/14659 ,  H01L27/1469 ,  H01L2223/54426

摘要： A radiation detector in which a semiconductor substrate to convert radiation into charges, a circuit board comprising a readout circuit to read out signals from pixels arranged on the substrate, and a bonding layer to bond the substrate and the circuit board are stacked is provided. Each of the pixels comprises an electrode arranged on a first surface on a side of the circuit board of the substrate. The readout circuit is arranged on a second surface on a side of the substrate of the circuit board, and is connected to a conductive pattern arranged on a third surface on an opposite side of the second surface of the circuit board. The electrode is electrically connected to the readout circuit via the conductive pattern and a second conductive member arranged in a through hole penetrating the circuit board and the bonding layer.