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    Apparatus comprising compensation capacitors
    1.
    发明授权
    Apparatus comprising compensation capacitors 有权

    公开(公告)号：US11637105B2

    公开(公告)日：2023-04-25

    申请号：US17449583

    申请日：2021-09-30

    申请人： Micron Technology, Inc.

    发明人： Shigeru Sugioka ,  Keizo Kawakita

    IPC分类号： H01L27/108 ,  H01L23/522 ,  H01L23/64 ,  H01L23/52 ,  H01L49/02

    摘要： An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts. The third interconnections are elongated over the dielectric materials and are configured to provide elongated portions as the upper electrodes of the compensation capacitors. Related methods, memory devices, and electronic systems are disclosed.

    Adapter board and method for forming same, packaging method, and package structure
    2.
    发明授权
    Adapter board and method for forming same, packaging method, and package structure 有权

    公开(公告)号：US11637059B2

    公开(公告)日：2023-04-25

    申请号：US17155450

    申请日：2021-01-22

    申请人： Semiconductor Manufacturing North China (Beijing) Corporation

    发明人： Cai Qiaoming ,  Yang Lie Yong ,  Chen Wei ,  Lu Xiao Yu

    IPC分类号： H01L23/498 ,  H01L23/64 ,  H01L49/02 ,  H01L21/48 ,  H01L23/00

    摘要： Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure. In the embodiments and implementations of the present disclosure, the capacitor is further formed in the adapter board, so that a process of forming the capacitor and a process of forming the adapter board are integrated, and an additional step of forming the capacitor is omitted, which is beneficial to reduce processes and improve the process integration, and is further beneficial to reduce process costs and shorten the production cycle. Moreover, the functional diversity of the adapter board is further improved, so that an application scenario of the adapter board is diversified.

    SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20230005833A1

    公开(公告)日：2023-01-05

    申请号：US17943215

    申请日：2022-09-13

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chun-Hung Chen ,  Ming-Tse Lin

    IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L27/01

    摘要： A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

    Semiconductor devices having a resistor structure with more refined coupling effect for improved linearity of resistance
    10.
    发明申请
    Semiconductor devices having a resistor structure with more refined coupling effect for improved linearity of resistance 有权

    公开(公告)号：US20220416009A1

    公开(公告)日：2022-12-29

    申请号：US17830348

    申请日：2022-06-02

    申请人： MediaTek Singapore Pte. Ltd.

    发明人： Lanxiang Wang ,  Zhigang Duan

    IPC分类号： H01L49/02 ,  H01L23/64

    摘要： A semiconductor device includes a first terminal, a second terminal positioned away from the first terminal, a first resistive segment coupled between the first terminal and the second terminal, a third terminal positioned away from the first terminal and the second terminal, a second resistive segment coupled between the second terminal and third terminal, a first floating plate disposed physically proximate the first resistive segment and including a first end coupled to one of the first terminal and the second terminal, and a second floating plate disposed physically proximate the second resistive segment and including a first end coupled to one of the second terminal and the third terminal.