公开(公告)号：US11632886B2

公开(公告)日：2023-04-18

申请号：US17065026

申请日：2020-10-07

申请人： CANON KABUSHIKI KAISHA

发明人： Mitsutoshi Hasegawa

IPC分类号： H01L21/304 ,  H01L23/10 ,  H01L23/24 ,  H01L23/498 ,  H01L25/03 ,  H01L25/16 ,  H05K13/04 ,  H01L23/00 ,  H01L21/50 ,  H01L21/48 ,  H01L27/146 ,  H05K3/34 ,  H01L21/60

摘要： A method of manufacturing an electronic module includes supplying paste to an electronic component and/or a wiring board. The paste includes solder powder and first resin. The method includes supplying second resin to the electronic component and/or the wiring board. The method includes placing one of the electronic component and the wiring board on another. The method includes curing the second resin to form a second resin portion. The method includes heating the paste to a temperature equal to or higher than a solder melting point after the second resin portion is formed. The method includes solidifying molten solder at a temperature lower than the solder melting point to form a solder portion that bonds the electronic component and the wiring board. The method includes curing the first resin after the solder portion is formed, to form a first resin portion.

公开(公告)号：US11587922B2

公开(公告)日：2023-02-21

申请号：US17026900

申请日：2020-09-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Fa Chen ,  Hsien-Wei Chen

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L25/03 ,  H01L21/56 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065

摘要： A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

公开(公告)号：US11362046B2

公开(公告)日：2022-06-14

申请号：US16887351

申请日：2020-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/03 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

摘要： Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.

公开(公告)号：US11348653B2

公开(公告)日：2022-05-31

申请号：US16458304

申请日：2019-07-01

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Seiko Amano ,  Kouhei Toyotaka ,  Hiroyuki Miyake ,  Aya Miyazaki ,  Hideaki Shishido ,  Koji Kusunoki

IPC分类号： G11C19/00 ,  G11C19/28 ,  H03K19/00 ,  G11C19/18 ,  H01L25/03 ,  H05K7/02 ,  G09G3/36 ,  H01L27/12

摘要： An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

公开(公告)号：US11270923B2

公开(公告)日：2022-03-08

申请号：US16789063

申请日：2020-02-12

申请人： SK hynix Inc.

发明人： Min Kyu Kang ,  Jae Hyun Son ,  Ji Hyeok Shin

IPC分类号： H01L23/34 ,  H01L23/367 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L25/03 ,  H01L23/373 ,  H01L23/433 ,  H01L23/16

摘要： A semiconductor package includes a first semiconductor chip and a second semiconductor chip which are disposed side-by-side on a surface of a package substrate. A heat insulation wall is disposed between the first semiconductor chip and the second semiconductor chip. The heat insulation wall thermally isolates the first semiconductor chip from the second semiconductor chip.

公开(公告)号：US11239205B2

公开(公告)日：2022-02-01

申请号：US16741003

申请日：2020-01-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chia Hu ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L25/03 ,  H01L25/18 ,  H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

摘要： A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

公开(公告)号：US11056373B2

公开(公告)日：2021-07-06

申请号：US14918189

申请日：2015-10-20

申请人： Apple Inc.

发明人： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

摘要： Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

公开(公告)号：US11018026B2

公开(公告)日：2021-05-25

申请号：US16699283

申请日：2019-11-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC分类号： H05K1/11 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14

摘要： A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.

公开(公告)号：US10854568B2

公开(公告)日：2020-12-01

申请号：US15647704

申请日：2017-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L23/538 ,  H01L25/03 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H01L25/18

摘要： A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US10734367B2

公开(公告)日：2020-08-04

申请号：US16232159

申请日：2018-12-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L25/03 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

摘要： A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.