公开(公告)号：US20250072011A1

公开(公告)日：2025-02-27

申请号：US18584426

申请日：2024-02-22

Applicant: SK hynix Inc.

Inventor： Jung Shik JANG ,  Seok Min CHOI ,  Rho Gyu KWAK ,  Won Geun CHOI ,  In Su PARK

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a first peripheral circuit having first page buffers is functionally divided into a cell region and a connection region. A first memory cell array positioned on the first peripheral circuit includes first bit lines that are electrically connected to the first page buffers. A second memory cell array positioned on the first memory cell array includes second bit lines, which are electrically connected to the first bit lines, respectively. The first peripheral circuit is able to make use of both memory arrays using connections between the two memory arrays.

公开(公告)号：US20250070104A1

公开(公告)日：2025-02-27

申请号：US18814476

申请日：2024-08-24

Applicant: Infineon Technologies AG

Inventor： Tomas Reiter ,  Dietmar Spltzer ,  Christoph Koch

IPC: H01L25/16 ,  H01L23/051 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52 ,  H01L25/065 ,  H10N52/00 ,  H10N59/00

Abstract: A power semiconductor module of a power electronic system includes: a power electronic substrate; a power semiconductor die arranged on and electrically coupled to a first side of the substrate; a plastic frame arranged at the first side and defining an interior volume of the module; and a load current contact electrically connected to the first side and partially exposed from the frame. The frame includes a recess above a side of the load current contact facing away from the substrate. A driver board arranged above the module includes circuitry configured to drive power circuitry of the module. A current sensor arranged on and electrically coupled to a side of the driver board facing the module is configured to detect an alternating current flowing through the load current contact. The sensor is arranged at least partially within the recess. The frame electrically isolates the sensor from the load current contact.

公开(公告)号：US20250070091A1

公开(公告)日：2025-02-27

申请号：US18942886

申请日：2024-11-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

公开(公告)号：US20250070090A1

公开(公告)日：2025-02-27

申请号：US18789675

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Dong Uk Lee ,  Raghukiran Sreeramaneni ,  Yen Chun Lee

IPC: H01L25/065 ,  H10B80/00

Abstract: A memory device is provided. The memory device includes a plurality of memory dies positioned in a stack, the stack including a first set of memory dies and a second set of memory dies. Each die in the first set includes a first plurality of channels in a first configuration that includes channels configured to operate in a first bandwidth mode and channels configured to operate in a second bandwidth mode. Each die in the second set includes a second plurality of channels in a second configuration that includes channels configured to operate in the second bandwidth mode.

公开(公告)号：US20250070086A1

公开(公告)日：2025-02-27

申请号：US18455928

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM ,  Manuel ALDRETE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A device includes a bottom substrate including first conductors, a top substrate including second conductors, and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and to the first conductors. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes second contacts electrically connected to the first contacts through the first conductors and third contacts electrically connected to the second conductors. The redistribution die also includes redistribution traces electrically connected to the second contacts and to the third contacts. The top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die.

公开(公告)号：US20250070074A1

公开(公告)日：2025-02-27

申请号：US18756361

申请日：2024-06-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroaki HOKAZONO

IPC: H01L23/00 ,  H01L23/057 ,  H01L23/31 ,  H01L23/36 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device, including an electrically conductive portion, and a terminal. The terminal includes a bonding portion that is of a flat plate shape and has: a rear surface bonded to the electrically conductive portion, and a front surface having an indentation formed thereon. The front surface has two opposite sides that are respectively a bonding front-end side and a bonding rear-end side. The indentation has two opposite sides that are respectively an indentation front-end side and an indentation rear-end side. The indentation front-end side is flush with the bonding front-end side. A length of the indentation rear-end side is shorter than a length of the bonding rear-end side.

公开(公告)号：US20250070072A1

公开(公告)日：2025-02-27

申请号：US18640576

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyo KIM ,  MINSOO KIM ,  SANG-SICK PARK

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor die, a first under-fill layer on an upper surface of the first semiconductor die, a second under-fill layer on the first under-fill layer, a second semiconductor die provided on the second under-fill layer, and a mold layer on side surfaces of the second semiconductor die, the second under-fill layer, and the upper surface of the first semiconductor die. The first semiconductor die includes a first substrate, a first redistribution pattern on the first substrate, a first redistribution dielectric layer provided on the first redistribution pattern, and a first dam on the first redistribution dielectric layer and along an edge of the first substrate, and the first under-fill layer contacts a side surface of the first dam.

公开(公告)号：US20250070065A1

公开(公告)日：2025-02-27

申请号：US18940493

申请日：2024-11-07

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wei Liu ,  Hongbin Zhu ,  Ziqun Hua ,  Ning Jiang ,  Wenyu Hua

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a second semiconductor structure. The second semiconductor structure includes an array of memory cells, each of the memory cells including a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

公开(公告)号：US20250069983A1

公开(公告)日：2025-02-27

申请号：US18726786

申请日：2023-01-03

Applicant: AMOSENSE CO., LTD.

Inventor： Jihyung LEE

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15 ,  H01L23/473 ,  H01L23/498 ,  H01L25/065

Abstract: The present invention relates to a ceramic substrate unit and a manufacturing method therefor. The ceramic substrate unit comprises: a ceramic substrate having metal layers on the upper and lower surfaces of the ceramic substrate; a heat dissipation spacer bonded to the upper metal layer of the ceramic substrate; and a heat sink bonded to the lower metal layer of the ceramic substrate, wherein the heat dissipation spacer is provided with an electrode in a region to which a semiconductor chip is bonded, so that the semiconductor chip may be bonded in the form of a flip chip.

公开(公告)号：US20250069980A1

公开(公告)日：2025-02-27

申请号：US18946959

申请日：2024-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wensen Hung ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Yu Chen ,  Tsung-Shu Lin ,  Chien-Yuan Huang ,  Chen-Hsiang Lao

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H01L23/495 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.