公开(公告)号：US20230137580A1

公开(公告)日：2023-05-04

申请号：US18146709

申请日：2022-12-27

申请人： Adeia Semiconductor Inc.

发明人： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC分类号： H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06

摘要： Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US11640964B2

公开(公告)日：2023-05-02

申请号：US17504721

申请日：2021-10-19

申请人： NXP USA, Inc.

发明人： Evgueniy Nikolov Stefanov ,  Pascal Kamel Abouda

IPC分类号： H01L27/13 ,  H01L49/02 ,  H01L27/08 ,  H01L23/522 ,  H01L29/94 ,  H01L27/06 ,  H01L27/12

摘要： There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:
wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric;
the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.

公开(公告)号：US20230130975A1

公开(公告)日：2023-04-27

申请号：US17508965

申请日：2021-10-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： KAI-PO SHANG ,  JUI-HSIU JAO

IPC分类号： H01L23/525 ,  H01L27/06

摘要： A semiconductor device with a fuse component is provided. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The he gate metal layer is configured to receive a voltage to change a resistivity between the gate metal layer and the active region.

公开(公告)号：US20230127508A1

公开(公告)日：2023-04-27

申请号：US17969920

申请日：2022-10-20

申请人： Infineon Technologies AG

发明人： Joachim Weyers ,  Franz Hirler

IPC分类号： G01K7/01 ,  H01L27/06 ,  H01L29/06

摘要： A semiconductor device includes a transistor array and a sense pad. The transistor array includes a plurality of transistor cells electrically connected in parallel between a source electrode and a drain structure. The drain structure is formed in a semiconductor portion based on a single-crystalline wide bandgap material. A sense element formed from the wide bandgap material includes at least one rectifying junction electrically connected between the sense pad and the source electrode.

公开(公告)号：US20230127197A1

公开(公告)日：2023-04-27

申请号：US17892660

申请日：2022-08-22

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hitoshi MATSUURA

IPC分类号： H01L27/06 ,  H01L29/739 ,  H01L21/265 ,  H01L29/66

摘要： A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate, and a first polysilicon film. The semiconductor substrate has a first main surface and a second main surface that is an opposite surface of the first main surface. The semiconductor substrate has a first portion and a second portion. The semiconductor substrate is a collector region arranged on the second main surface located in the first portion, a cathode region arranged on the second main surface located in the second portion, a drift region arranged on the collector region and the cathode region, an emitter region arranged on the first main surface located in the first portion, a base region arranged between the emitter region and the collector region, and an anode region arranged on the first main surface located in the second portion.

公开(公告)号：US11637100B2

公开(公告)日：2023-04-25

申请号：US17400095

申请日：2021-08-11

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Qiying Wong ,  Handoko Linewih ,  Yudi Setiawan ,  Chengang Feng ,  Siow Lee Chwa

IPC分类号： H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L27/01

摘要： The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

公开(公告)号：US11631688B2

公开(公告)日：2023-04-18

申请号：US17540224

申请日：2021-12-01

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Jun Liu ,  Weihua Cheng

IPC分类号： H01L27/11 ,  H01L27/1157 ,  H01L21/50 ,  H01L23/00 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11578 ,  G11C14/00 ,  G11C16/04 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L21/02 ,  H01L21/20 ,  H01L21/76 ,  H01L21/822 ,  H01L25/065

摘要： Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

公开(公告)号：US11631586B2

公开(公告)日：2023-04-18

申请号：US16914169

申请日：2020-06-26

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

发明人： Paul M. Enquist ,  Gaius Gillman Fountain

IPC分类号： H01L21/20 ,  H01L23/498 ,  H01L21/768 ,  H01L25/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

摘要： A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

公开(公告)号：US20230112644A1

公开(公告)日：2023-04-13

申请号：US17490950

申请日：2021-09-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC分类号： H01L27/06 ,  H01L49/02 ,  H01L21/285

摘要： Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US11626397B2

公开(公告)日：2023-04-11

申请号：US17006265

申请日：2020-08-28

申请人： SANDISK TECHNOLOGIES LLC

发明人： Hokuto Kodate ,  Hiroyuki Ogawa ,  Dai Iwata ,  Mitsuhiro Togo

IPC分类号： H01L27/06 ,  H01L21/8234

摘要： At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.