公开(公告)号：US12237327B2

公开(公告)日：2025-02-25

申请号：US17523816

申请日：2021-11-10

Applicant: pSemi Corporation

Inventor： Shashi Samal ,  Matt Allison

IPC: H01L27/085 ,  H01L21/822 ,  H01L27/02

Abstract: Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

公开(公告)号：US12094963B2

公开(公告)日：2024-09-17

申请号：US17317263

申请日：2021-05-11

Applicant: Infineon Technologies Austria AG

Inventor： Oliver Haeberlen ,  Walter Rieger

IPC: H01L29/778 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/1066 ,  H01L29/41766 ,  H01L29/432

Abstract: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.

公开(公告)号：US12074093B2

公开(公告)日：2024-08-27

申请号：US17630766

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu Yanagihara ,  Takahiro Sato ,  Hiroto Yamagiwa ,  Masahiro Hikita

IPC: H01L21/02 ,  H01L23/48 ,  H01L23/482 ,  H01L27/085 ,  H01L29/778 ,  H01L27/06 ,  H02M3/335

CPC classification number: H01L23/481 ,  H01L23/4824 ,  H01L27/085 ,  H01L29/7786 ,  H01L27/0605 ,  H02M3/33569

Abstract: An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

公开(公告)号：US20240266348A1

公开(公告)日：2024-08-08

申请号：US18105586

申请日：2023-02-03

Applicant: Wolfspeed, Inc.

Inventor： Fabian Radulescu ,  Basim Noori ,  Scott Sheppard ,  Qianli Mu ,  Jeremy Fisher ,  Dan Namishia

IPC: H01L27/085 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L27/085 ,  H01L23/528 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/16227

Abstract: A transistor device includes a substrate and a plurality of transistor unit cells arranged in parallel on the substrate. Each of the transistor unit cells includes a source contact, a drain contact, and a gate finger between the source contact and the drain contact. The gate finger extends in a first direction and has a first end and a second end. The transistor device further includes a first solder bump on the transistor device that is within a periphery of the active region of the device and is electrically connected to the gate finger of a first one of the unit cells at a feed point that is between the first end and the second end of the gate finger.

公开(公告)号：US12034072B2

公开(公告)日：2024-07-09

申请号：US17190559

申请日：2021-03-03

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Yueying Liu ,  Saptharishi Sriram ,  Scott Sheppard ,  Jennifer Gao

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/085 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F3/42 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L27/085 ,  H01L29/0696 ,  H01L29/42316 ,  H01L29/7786 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F3/211 ,  H03F3/423 ,  H01L29/2003 ,  H03F2200/366

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

公开(公告)号：US20240047451A1

公开(公告)日：2024-02-08

申请号：US17626117

申请日：2021-08-06

Applicant: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.

Inventor： Hui YAN ,  Sichao LI

IPC: H01L27/02 ,  H01L29/20 ,  H01L27/085 ,  H01L21/8252 ,  H01L21/76 ,  H01L29/417

CPC classification number: H01L27/0207 ,  H01L29/2003 ,  H01L27/085 ,  H01L21/8252 ,  H01L21/7605 ,  H01L29/4175 ,  H01L29/778

Abstract: A nitride-based semiconductor integrated circuit (IC) chip is provided. The IC chip comprises: a substrate; intra-transistor isolation regions formed in a surface of the substrate for defining power domains respectively for transistors integrated in the IC chip; an epitaxial body layer disposed over the substrate and the intra-transistor isolation regions; a first and a second nitride-based layers disposed above the epitaxial body layer. The epitaxial body layer and the substrate are formed of a same material and each of the one or more intra-transistor isolation regions is implanted to have a doping polarity opposite to a doping polarity of the substrate. By the implementation of the epitaxial body layer over the isolation regions, the quality of the heterojunction formed between the nitride-based semiconductor layers can be guaranteed as the impact of implantation of the isolation regions to the formation of heterojunction interface can be eliminated.

公开(公告)号：US20240047201A1

公开(公告)日：2024-02-08

申请号：US18258784

申请日：2021-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

Inventor： Guy FEUILLET ,  Thierry BOUCHET ,  Matthew CHARLES ,  Roy DAGHER ,  Jesus ZUNIGA PEREZ

IPC: H01L21/02 ,  H01L21/78 ,  H01L29/78 ,  H01L29/66 ,  H01L29/872 ,  H01L29/868 ,  H01L21/8252 ,  H01L27/08 ,  H01L27/085

CPC classification number: H01L21/02505 ,  H01L21/7806 ,  H01L29/7827 ,  H01L29/66212 ,  H01L29/872 ,  H01L29/868 ,  H01L29/66522 ,  H01L29/66204 ,  H01L21/0254 ,  H01L21/0245 ,  H01L21/02447 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02458 ,  H01L21/02381 ,  H01L21/8252 ,  H01L27/0814 ,  H01L27/085

Abstract: A method for producing a vertical component comprising with the basis of a III-N material, comprising providing platelets made of the III-N material obtained by epitaxy on pads, the platelets comprise at least first and second layers doped and stacked on one another in a vertical direction. The method further includes the production of a first electrode and the production of a second electrode located on the platelet and configured such that a current passing from one electrode to the other passes through at least the second layer in all of its thickness, the thickness being taken in the vertical direction.

公开(公告)号：US20230282639A1

公开(公告)日：2023-09-07

申请号：US18317440

申请日：2023-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Yi-Hsun CHIU

IPC: H01L27/085 ,  H01L27/092 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/085 ,  H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/118 ,  H01L21/823892

Abstract: A method of forming an integrated circuit structure includes generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure. The generating the first well layout pattern includes generating a first layout pattern having a first width, and corresponding to fabricating a first portion of the first well, and generating a second layout pattern having a second width and corresponding to fabricating a second portion of the first well. The method further includes generating a first implant layout pattern having a third width and corresponding to fabricating a first set of implants in the first portion of the first well, generating a second implant layout pattern having a fourth width and corresponding to fabricating a second set of implants in the second portion of the first well, and manufacturing the integrated circuit structure based on the above layout patterns.

公开(公告)号：US11735485B2

公开(公告)日：2023-08-22

申请号：US17345659

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

IPC: H01L27/098 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/085 ,  H01L29/732 ,  H01L29/808 ,  H01L29/861 ,  H01L29/93 ,  H01L27/07 ,  H01L29/06

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/732 ,  H01L29/7327 ,  H01L29/808 ,  H01L29/861 ,  H01L29/93 ,  H01L27/07 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

公开(公告)号：US11705451B2

公开(公告)日：2023-07-18

申请号：US17394991

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inwon Park ,  Bosoon Kim ,  Jongsoon Park

IPC: H01L27/088 ,  H01L21/762 ,  H01L27/02 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L27/085 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L27/0207

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.