公开(公告)号：US11581332B2

公开(公告)日：2023-02-14

申请号：US17226056

申请日：2021-04-08

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Li Hong Xiao

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11563

摘要： Embodiments of a three-dimensional (3D) memory device are provided. The 3D memory device includes a stack structure over a substrate. The stack structure includes a plurality of conductor layers insulated from one another by a gate-to-gate dielectric structure. The gate-to-gate dielectric structure includes a gate-to-gate dielectric layer between adjacent conductor layers along a vertical direction perpendicular to a top surface of the substrate. The 3D memory device also includes a channel structure extending in the stack structure. The channel structure includes a memory layer that protrudes towards the gate-to-gate dielectric layer.

公开(公告)号：US20220328115A1

公开(公告)日：2022-10-13

申请号：US17716122

申请日：2022-04-08

申请人： Chen-Feng CHANG

发明人： Chen-Feng CHANG ,  Tien-Sheng CHAO

IPC分类号： G11C17/12 ,  G11C16/04 ,  G11C11/56 ,  H01L27/112 ,  H01L27/11563

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

公开(公告)号：US20210083069A1

公开(公告)日：2021-03-18

申请号：US16806146

申请日：2020-03-02

申请人： KIOXIA CORPORATION

发明人： Mitsuo IKEDA ,  Daisuke IKENO ,  Akihiro KAJITA

IPC分类号： H01L29/51 ,  H01L21/28 ,  H01L27/11563

摘要： According to one embodiment, a semiconductor device includes a substrate, a plurality of insulating films and a plurality of electrode films provided alternately on the substrate. The semiconductor device further includes a first insulating film, a first charge storage film, a third insulating film, a second charge storage film, a second insulating film, and a first semiconductor film that are sequentially provided along at least one side surface of each of the electrode films. The first charge storage film includes either (i) molybdenum, or (ii) titanium and nitrogen, and the second charge storage film includes a semiconductor film.

公开(公告)号：US10886288B2

公开(公告)日：2021-01-05

申请号：US16454914

申请日：2019-06-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hongsoo Kim ,  Hyunmog Park ,  Joongshik Shin

IPC分类号： H01L27/11551 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/06 ,  H01L27/11578 ,  H01L21/822 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11514

摘要： A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.

公开(公告)号：US20200373164A1

公开(公告)日：2020-11-26

申请号：US16417542

申请日：2019-05-20

申请人： UNITED MICROELECTRONICS CORP.

发明人： WEI XU ,  WENBO DING ,  Yu-Yang Chen ,  Wang Xiang

IPC分类号： H01L21/28 ,  H01L27/11563 ,  H01L21/033

摘要： A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

公开(公告)号：US10790364B2

公开(公告)日：2020-09-29

申请号：US16240366

申请日：2019-01-04

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC分类号： H01L21/00 ,  H01L21/28 ,  G11C16/04 ,  H01L29/51 ,  H01L29/792 ,  H01L27/11563 ,  H01L21/02 ,  H01L29/423

摘要： A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

公开(公告)号：US10515797B2

公开(公告)日：2019-12-24

申请号：US16031535

申请日：2018-07-10

申请人： TOSHIBA MEMORY CORPORATION

发明人： Kazuhito Furumoto ,  Keisuke Kikutani ,  Soichi Yamazaki

IPC分类号： H01L21/02 ,  H01L27/11563 ,  H01L21/302 ,  H01L21/033 ,  H01L21/28

摘要： According to one embodiment, a method for producing a semiconductor device includes forming a first film on a substrate. A second film is formed on the first film. A recess is formed in the second film. First processing by which a third film is formed on the second film to form a side face of the recess with the second film and second processing by which the first film exposed in the recess is processed by using the second and third films, are executed one or more times. In relation to an N-th (N is an integer greater than or equal to 1) first processing, before the third film is formed on the second film, a surface inclined with respect to the side face of the recess is formed above the side face of the recess.

公开(公告)号：US10446656B2

公开(公告)日：2019-10-15

申请号：US15376282

申请日：2016-12-12

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Igor Polishchuk ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  H01L29/66 ,  B82Y10/00 ,  H01L21/28 ,  H01L27/11526 ,  G11C16/04 ,  H01L27/11563 ,  H01L29/49 ,  H01L21/02 ,  H01L29/06 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575

摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.

公开(公告)号：US20190157286A1

公开(公告)日：2019-05-23

申请号：US16189319

申请日：2018-11-13

申请人： Cypress Semiconductor Corporation

发明人： Krishnaswamy Ramkumar

IPC分类号： H01L27/11568 ,  H01L29/51 ,  H01L29/167 ,  H01L29/792 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11563 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11573

CPC分类号： H01L27/11568 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/823462 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/167 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

公开(公告)号：US10283517B2

公开(公告)日：2019-05-07

申请号：US15703006

申请日：2017-09-13

申请人： Toshiba Memory Corporation

发明人： Takuo Ohashi ,  Fumiki Aiso

IPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11514 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11556

摘要： According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.