公开(公告)号：US12106030B2

公开(公告)日：2024-10-01

申请号：US17452357

申请日：2021-10-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hiranmay Biswas ,  Chung-Hsing Wang ,  Kuo-Nan Yang ,  Yi-Kan Cheng

IPC分类号： G06F30/394 ,  G06F30/398 ,  H01L27/02 ,  G06F119/06 ,  H01L27/118

CPC分类号： G06F30/394 ,  G06F30/398 ,  H01L27/0207 ,  G06F2119/06 ,  H01L27/11807

摘要： A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

公开(公告)号：US12094882B2

公开(公告)日：2024-09-17

申请号：US17719052

申请日：2022-04-12

申请人： Socionext Inc.

发明人： Hideyuki Komuro ,  Toshio Hino ,  Tomoya Tsuruta

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L2027/11881

摘要： In a power line structure for supplying power to standard cells, buried power lines extending in the X direction are placed at a given spacing in the Y direction. A local power line extending in the Y direction is connected with the buried power lines. Metal power lines extending in the X direction are formed in an upper-layer metal interconnect layer and connected with the local power line. The spacing of placement of the metal power lines in the Y direction is greater than the spacing of placement of the buried power lines.

公开(公告)号：US20240297167A1

公开(公告)日：2024-09-05

申请号：US18176551

申请日：2023-03-01

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Brent A. Anderson ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  David Wolpert

IPC分类号： H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC分类号： H01L27/0207 ,  H01L21/76877 ,  H01L27/11807 ,  H01L2027/11831

摘要： A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

公开(公告)号：US12080805B2

公开(公告)日：2024-09-03

申请号：US18358689

申请日：2023-07-25

申请人： SOCIONEXT INC.

发明人： Hiroyuki Shimbo

IPC分类号： H01L27/00 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/06 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/0207 ,  H01L2027/11874 ,  H01L27/1203

摘要： Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire PET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US12068325B2

公开(公告)日：2024-08-20

申请号：US18155386

申请日：2023-01-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jung Ho Do

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11851 ,  H01L2027/11875 ,  H01L2027/11881

摘要： A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1st circuit including at least one VFET and provided over at least one gate grid; and a 2nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1st circuit, wherein a gate of the VFET of the 1st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2nd circuit, and the 1st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

公开(公告)号：US12068187B2

公开(公告)日：2024-08-20

申请号：US18424790

申请日：2024-01-27

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US12056432B2

公开(公告)日：2024-08-06

申请号：US18300142

申请日：2023-04-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fong-yuan Chang ,  Chun-Chen Chen ,  Sheng-Hsiung Chen ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Jung-Chan Yang ,  Lee-Chung Lu ,  Po-Hsiang Huang

IPC分类号： G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118

CPC分类号： G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

摘要： The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20240243133A1

公开(公告)日：2024-07-18

申请号：US18155354

申请日：2023-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhon-Jhy LIAW

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L2027/11853

摘要： A method for manufacturing a semiconductor structure includes defining active areas extending in an X-direction, arranged in a Y-direction, and on a substrate. Each of the active areas has nanostructures. The method further includes forming dummy gate structures across the active areas in the Y-direction, forming merged source/drain features in the active areas and on opposite sides of the dummy gate structures in the X-direction, forming dielectric structures in the active areas to cut each of the merged source/drain features into a first source/drain feature and a second source/drain feature, and to cut each of the dummy gate structures into segments, and replacing the segments of the dummy gate structures with gate structures wrapping around the nanostructures in the active areas. The dielectric structures are in contact with sidewalls of the first source/drain features, the second source/drain features, and the gate structures.

公开(公告)号：US20240234424A1

公开(公告)日：2024-07-11

申请号：US18417446

申请日：2024-01-19

申请人： Adeia Semiconductor Inc.

发明人： Javier A. DeLaCruz ,  Don Draper ,  Jung Ko ,  Steven L. Teig

IPC分类号： H01L27/118 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L27/11807 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2027/11838 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

摘要： The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

公开(公告)号：US20240213252A1

公开(公告)日：2024-06-27

申请号：US18086229

申请日：2022-12-21

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Ruilong Xie

IPC分类号： H01L27/118 ,  H03K17/693

CPC分类号： H01L27/11807 ,  H03K17/693 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11885

摘要： Integrated circuits and related logic circuits and structures employing VTFET logic devices. In particular, during middle-of-line (MOL) processing, method steps are employed for forming two-level MOL contact connector structures below first (M1) metallization level wiring formed during subsequent BEOL processing. Using damascene and subtractive metal etch techniques, respective MOL contact connector structures at two levels are formed with a second level above a first level contact. These contact connector structures at two levels below M1 metallization level can provide cross-connections to VTFET devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access. The flexible MOL cross-connections made below M1 metallization level provides for much improved M1 and M2 wirability and enable semiconductor circuit layouts that allow for improved cell size reduction without creating significant connection issues at high wiring levels thereby increasing circuit design flexibility.