公开(公告)号：US20250072069A1

公开(公告)日：2025-02-27

申请号：US18455446

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Desalegne B. Teweldebrhan ,  Shengsi Liu ,  Saurabh Acharya ,  Marko Radosavljevic ,  Richard Schenker

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via that is recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

公开(公告)号：US20250072042A1

公开(公告)日：2025-02-27

申请号：US18376450

申请日：2023-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Hsin Chen ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-cheng Su

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

公开(公告)号：US12237403B2

公开(公告)日：2025-02-25

申请号：US18298055

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chih-Shan Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

公开(公告)号：US20250063796A1

公开(公告)日：2025-02-20

申请号：US18434084

申请日：2024-02-06

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Hiroki NEMOTO ,  Tsuyoshi KACHI ,  Hiroaki KATOU ,  Kazuyuki SATO ,  Toshifumi NISHIGUCHI

IPC: H01L29/417 ,  H01L21/04 ,  H01L29/08 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device according to an embodiment includes: a first electrode; a first semiconductor region of a first conductive type provided on the first electrode; a second semiconductor region of a second conductive type provided on the first semiconductor region; a third semiconductor region of a first conductive type provided on the second semiconductor region; a gate electrode provided in the second semiconductor region via a gate insulating film; a contact portion having a first portion and a second portion; and a second electrode electrically connected to the contact portion. The first portion is aligned with the third semiconductor region and a part of the second semiconductor region, and the second portion is provided at a lower end of the first portion and has a width larger than a width of the first portion at an upper end of the third semiconductor region.

公开(公告)号：US12230674B2

公开(公告)日：2025-02-18

申请号：US18358282

申请日：2023-07-25

Applicant: IceMos Technology Limited

Inventor： Kiraneswar Muthuseenu ,  Samuel Anderson ,  Takeshi Ishiguro

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm−3 and 1.5×1020 cm−3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.

公开(公告)号：US12230559B2

公开(公告)日：2025-02-18

申请号：US18329347

申请日：2023-06-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. Carney ,  Jefferson W. Hall ,  Michael J. Seddon

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L27/146 ,  H01L29/08 ,  H02M3/158 ,  H01L23/14 ,  H01L23/15 ,  H01L23/367

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

公开(公告)号：US20250056876A1

公开(公告)日：2025-02-13

申请号：US18516478

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Huan HSIN ,  Ying-Han CHIOU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: The present disclosure describes a semiconductor device having an identification device for chip identification. The semiconductor structure includes first and second channel structures on a substrate, a gate structure on the first and second channel structures, an epitaxial structure on the first and second channel structures, and a first source/drain (S/D) contact structure on the first channel structure. The epitaxial structure is at a first side of the gate structure and the first S/D contact structure is at a second side of the gate structure opposite to the first side. The semiconductor structure further includes a second S/D contact structure on the second channel structure. The second S/D contact structure is at the second side of the gate structure.

公开(公告)号：US20250056861A1

公开(公告)日：2025-02-13

申请号：US18583006

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  MYUNG GIL KANG ,  DONGWON KIM ,  BEOMJIN PARK ,  DONGSUK SHIN ,  HYUN-KWAN YU ,  WOOSUK CHOI ,  SEUNGPYO HONG

IPC: H01L29/66 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other, a source/drain pattern electrically connected to the plurality of semiconductor patterns, an inner gate electrode between adjacent first and second semiconductor patterns of the plurality of semiconductor patterns, an inner gate insulating layer between the inner gate electrode and the first and second semiconductor patterns, an inner high-k dielectric layer between the inner gate electrode and the inner gate insulating layer, and an inner spacer between the inner gate insulating layer and the source/drain pattern. As the inner gate insulating layer includes an inner gate spacer, the inner gate electrode may stably fill the inner gate space. As a result, the electrical characteristics of the semiconductor device may be improved.

公开(公告)号：US20250056840A1

公开(公告)日：2025-02-13

申请号：US18366937

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen CHUANG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate. Semiconductor channel layers are over the substrate. A gate structure wraps around each of the semiconductor channel layers. Source/drain epitaxial structures are on opposite sides of the gate structure. Epitaxial seed layers are below the source/drain epitaxial structures, respectively, in which a lattice constant of the epitaxial seed layers is different from a lattice constant of the source/drain epitaxial structures. Isolation layers are over the substrate and vertically below the epitaxial seed layers, respectively.

公开(公告)号：US12225740B2

公开(公告)日：2025-02-11

申请号：US18435609

申请日：2024-02-07

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Srijit Mukherjee ,  Vinay Bhagwat ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/8238 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10D1/47 ,  H10D30/62 ,  H10D30/69 ,  H10D62/13 ,  H10D64/01 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.