公开(公告)号：US20250072034A1

公开(公告)日：2025-02-27

申请号：US18798916

申请日：2024-08-09

Applicant: ROHM CO., LTD.

Inventor： Yosuke HATA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron travelling layer; an electron supply layer; a gate layer, formed on the electron supply layer; a gate electrode, formed on the gate layer; and a passivation layer, having a source opening and a drain opening. The electron travelling layer includes: a first portion, located under the gate layer; and a second portion, located between the gate layer and the source opening, and located between the gate layer and the drain opening. The electron supply layer includes: a first electron supply layer, formed on the first portion and located below the gate layer; and a second electron supply layer, formed on the second portion and connected to the first electron supply layer.

公开(公告)号：US20250072032A1

公开(公告)日：2025-02-27

申请号：US18484430

申请日：2023-10-10

Applicant: Industrial Technology Research Institute

Inventor： Shin-Yi Huang ,  Hua-Mao Chen ,  Chih-Hung Yen

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417

Abstract: A semiconductor power device includes a substrate, a channel layer, a barrier layer, a gate, a source, and a drain. The channel layer is located on the substrate. The barrier layer is located on the channel layer and includes a first region and a second region outside the first region. There is a first compound in the first region and a second compound in the second region. The first compound and the second compound each have an aluminum atom of a different ratio, and the aluminum composition ratio of the first compound is less than the aluminum composition ratio of the second compound. The ratio consists of a plurality of different atoms in the first compound and the second compound.

公开(公告)号：US20250072020A1

公开(公告)日：2025-02-27

申请号：US18813593

申请日：2024-08-23

Applicant: ROHM Co., LTD.

Inventor： Akira Sagawa

IPC: H01L29/872 ,  H01L23/00 ,  H01L29/20 ,  H01L29/24 ,  H01L29/417 ,  H01L29/47 ,  H01L29/868

Abstract: Provided is a semiconductor package including a Si substrate, a drift layer, a buffer layer, an anode electrode, a trench, a semiconductor apparatus, an anode terminal, a cathode terminal, and a sealing resin.

公开(公告)号：US12237395B2

公开(公告)日：2025-02-25

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/768 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US12237169B2

公开(公告)日：2025-02-25

申请号：US17714204

申请日：2022-04-06

Applicant: The Government of the United States of America, as Represented by the Secretary of the Navy

Inventor： Boris N. Feigelson ,  Alan G. Jacobs

IPC: H01L21/00 ,  H01L21/265 ,  H01L29/20 ,  H01L29/207 ,  H01L29/24

Abstract: Methods for efficient doping of wide-bandgap (WBG) and ultrawide-bandgap (UWBG) semiconductors by implantation, and WBG and UWBG semiconductors made using the disclosed methods. A p-type semiconductor region is formed by implanting specified acceptor and donor co-dopant atoms in a predetermined ratio, e.g., two acceptors to one donor (ADA), into the semiconductor lattice. An n-type type semiconductor region is by implanting specified donor and acceptor co-dopant atoms in a predetermined ratio, e.g., two donors to one acceptor (DAD), into the semiconductor lattice. Compensator atoms are also implanted into the lattice to complete formula units in the crystal lattice structure and preserve the stoichiometry of the semiconductor material. The doped material is then annealed to activate the dopants and repair any damage to the lattice that might have occurred during implantation.

公开(公告)号：US20250063756A1

公开(公告)日：2025-02-20

申请号：US18938715

申请日：2024-11-06

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Nicholas Stephen Dellas ,  Qhalid Fareed

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

公开(公告)号：US12230689B2

公开(公告)日：2025-02-18

申请号：US17145507

申请日：2021-01-11

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.

公开(公告)号：US12230636B2

公开(公告)日：2025-02-18

申请号：US18198195

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong Chern

IPC: H01L27/095 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/778 ,  H03K17/16

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

公开(公告)号：US12224721B2

公开(公告)日：2025-02-11

申请号：US17488920

申请日：2021-09-29

Applicant: Qorvo US, Inc.

Inventor： Joel Lawrence Dawson ,  Gangadhar Burra ,  Frederick L. Martin ,  Mark Briffa ,  Rached Hajjii ,  Amin Shahverdi ,  Elias Reese ,  Nikolaus Klemmer ,  Jeffrey Gengler

IPC: H03F3/24 ,  H01L29/20 ,  H03F1/02 ,  H03F1/30

Abstract: A power amplifier with a quasi-static drain voltage adjustment is provided that has a transistor that is made from Gallium Nitride (GaN). In an exemplary aspect, the transistor is a field-effect transistor (FET) having a source, gate, and drain. The transistor is tested for process variations. Based on detected process variations, a microcontroller may raise a drain voltage to increase output power capability. Power capability of the power amplifier scales as the square of the drain voltage, so small adjustments are sufficient to offset the slow process corner while maintaining reliability.

公开(公告)号：US12224333B2

公开(公告)日：2025-02-11

申请号：US17842814

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

Abstract: An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.