公开(公告)号：US20240363710A1

公开(公告)日：2024-10-31

申请号：US18641457

申请日：2024-04-22

申请人： ROHM CO., LTD.

发明人： Kenta WATANABE

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/7813

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a first gate trench and a second gate trench, arranged along a first direction in a plan view seen from a direction perpendicular to the upper surface, and extending along a second direction intersecting the first direction; a third gate trench, extending along the first direction from the first gate trench toward the second gate trench and forming a first gap with the second gate trench; a fourth gate trench, spaced apart from the third gate trench along the second direction, extending along the first direction from the second gate trench toward the first gate trench and forming a second gap with the first gate trench; a field plate trench, disposed in a cell region surrounded by the first to fourth gate trenches; and gate electrodes, disposed within the first to fourth gate trenches.

公开(公告)号：US20240363423A1

公开(公告)日：2024-10-31

申请号：US18767533

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wan-Yao WU ,  Chang-Yun Chang ,  Ming-Chang Wen

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L21/823437 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/401

摘要： The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

公开(公告)号：US12132108B2

公开(公告)日：2024-10-29

申请号：US17876795

申请日：2022-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chih Su ,  Ruey-Hsin Liu ,  Pei-Lun Wang ,  Jia-Rui Lee ,  Jyun-Guan Jhou

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66659 ,  H01L29/7831

摘要： The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

公开(公告)号：US12132088B2

公开(公告)日：2024-10-29

申请号：US17353051

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chien Liu ,  Yao-Chung Chang ,  Chun Lin Tsai

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/41766 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7783

摘要： Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

公开(公告)号：US12132087B2

公开(公告)日：2024-10-29

申请号：US17582726

申请日：2022-01-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Kai Chuang

IPC分类号： H01L27/108 ,  H01L29/40 ,  H10B12/00

CPC分类号： H01L29/401 ,  H10B12/482

摘要： The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: forming a bit line over a substrate; forming a first spacer layer over and conformal to the bit line; forming a sacrificial layer over and conformal to the first spacer layer; forming a second spacer layer over and conformal to the sacrificial layer; forming a mask layer covering a lower portion of the second spacer layer; removing an upper portion of the second spacer layer; removing the sacrificial layer; and forming a third spacer layer over the first spacer layer and the second spacer layer, thereby forming a first air gap surrounded by the lower portion of the second spacer layer.

公开(公告)号：US12132000B2

公开(公告)日：2024-10-29

申请号：US17460168

申请日：2021-08-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Cherng-Shiaw Tsai ,  Kuang-Wei Yang ,  Hsin-Yen Huang ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/53276 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

摘要： An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.

公开(公告)号：US12131951B2

公开(公告)日：2024-10-29

申请号：US17452450

申请日：2021-10-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chuxian Liao ,  Jie Liu ,  Jun He ,  Lixia Zhang ,  Zhan Ying

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/53228 ,  H01L24/94

摘要： Embodiments of the present disclosure propose a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other.

公开(公告)号：US12131949B2

公开(公告)日：2024-10-29

申请号：US18362676

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Yu Chen ,  Chung-Liang Cheng

IPC分类号： H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L21/76879 ,  H01L21/2254 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76882 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/31122 ,  H01L21/76831 ,  H01L29/456

摘要： A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US20240355896A1

公开(公告)日：2024-10-24

申请号：US18760602

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

摘要： A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US12125923B2

公开(公告)日：2024-10-22

申请号：US17191173

申请日：2021-03-03

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jaroslav Pjencak ,  Moshe Agam ,  Johan Camiel Julia Janssens

IPC分类号： H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/861 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/76291 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/6609 ,  H01L29/7824

摘要： A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.