公开(公告)号：US20240363750A1

公开(公告)日：2024-10-31

申请号：US18771200

申请日：2024-07-12

申请人： Renesas Electronics Corporation

发明人： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

CPC分类号： H01L29/7838 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H03F3/45179

摘要： In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363404A1

公开(公告)日：2024-10-31

申请号：US18767722

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng CHEN ,  Tang-Kuei CHANG ,  Yee-Chia YEO ,  Huicheng CHANG ,  Wei-Wei LIANG ,  Ji CUI ,  Fu-Ming HUANG ,  Kei-Wei CHEN ,  Liang-Yin CHEN

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L21/76859 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/7851

摘要： The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US12132000B2

公开(公告)日：2024-10-29

申请号：US17460168

申请日：2021-08-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Cherng-Shiaw Tsai ,  Kuang-Wei Yang ,  Hsin-Yen Huang ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/53276 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

摘要： An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.

公开(公告)号：US12131949B2

公开(公告)日：2024-10-29

申请号：US18362676

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Yu Chen ,  Chung-Liang Cheng

IPC分类号： H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L21/76879 ,  H01L21/2254 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76882 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/31122 ,  H01L21/76831 ,  H01L29/456

摘要： A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US20240355936A1

公开(公告)日：2024-10-24

申请号：US18327081

申请日：2023-06-01

申请人： United Microelectronics Corp.

发明人： Boon Keat Toh ,  Chih-Hsin Chang ,  Szu Han Wu ,  Chi Ren

IPC分类号： H01L29/788 ,  H01L29/45 ,  H01L29/66 ,  H10B41/35

CPC分类号： H01L29/788 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66825 ,  H10B41/35

摘要： Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate having a first memory region. The first memory region includes a first dielectric layer, a first floating gate, a first inter-gate dielectric layer, a control gate and a first contact. The first dielectric layer is disposed on the substrate. The first floating gate is disposed on the first dielectric layer. The first inter-gate dielectric layer is disposed on the first floating layer. The control gate is disposed on the first inter-gate dielectric layer. The first contact penetrates through the first control gate and the first inter-gate dielectric layer and is landed on the first floating gate.

公开(公告)号：US20240355914A1

公开(公告)日：2024-10-24

申请号：US18759611

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Ching CHENG ,  Hung-Li CHIANG ,  Chun-Chieh LU ,  Ming-Yang LI ,  Tzu- Chiang CHEN

IPC分类号： H01L29/76 ,  H01L29/04 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7606 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/454 ,  H01L29/66795 ,  H01L29/785

摘要： A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

公开(公告)号：US20240347343A1

公开(公告)日：2024-10-17

申请号：US18292031

申请日：2022-02-15

申请人： NATIONAL UNIVERSITY CORPORATION TOKAI NATIONAL HIGHER EDUCATION AND RESEARCH SYSTEM

发明人： Manato DEKI ,  Shun LU ,  Hiroshi AMANO ,  Yoshio HONDA ,  Atsushi TANAKA ,  Yuta ITO

IPC分类号： H01L21/285 ,  H01L21/265 ,  H01L21/266 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L21/28575 ,  H01L21/2654 ,  H01L21/266 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

摘要： A technology is provided to form p-type regions and to effectively reduce a contact resistance between the p-type region and an electrode. One embodiment of a nitride semiconductor device manufacturing method may include a magnesium layer formation step of forming a magnesium layer that comprises magnesium as a major component on a surface of a nitride semiconductor substrate. The method may include an annealing step of annealing the nitride semiconductor substrate on which the magnesium layer is formed.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240332392A1

公开(公告)日：2024-10-03

申请号：US18737616

申请日：2024-06-07

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.