利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2245 条记录 (耗时 0.029 秒)

    TRANSISTOR FEEDBACK CAPACITANCE REDUCTION
    1.
    发明公开
    TRANSISTOR FEEDBACK CAPACITANCE REDUCTION 审中-公开

    公开(公告)号：US20240363742A1

    公开(公告)日：2024-10-31

    申请号：US18309320

    申请日：2023-04-28

    申请人： MACOM Technology Solutions Holdings, Inc.

    发明人： Debdas Pal ,  Parshant Kumar ,  Stephen Bilotta ,  Timothy E. Boles

    IPC分类号： H01L29/737 ,  H01L29/06

    CPC分类号： H01L29/737 ,  H01L29/0619

    摘要： The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12040323B2

    公开(公告)日：2024-07-16

    申请号：US17394252

    申请日：2021-08-04

    申请人： Murata Manufacturing Co., Ltd.

    发明人： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya ,  Kenji Sasaki

    IPC分类号： H01L27/06 ,  H01L29/737 ,  H03F3/19 ,  H03F3/21

    CPC分类号： H01L27/0647 ,  H01L29/737 ,  H03F3/19 ,  H03F3/21

    摘要： Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than ½ of a shorter one of distances between the first cell being looked at and adjacent cells.

    METHOD OF MANUFACTURING A SILICON BIPOLAR JUNCTION TRANSISTOR, AND A BJT
    4.
    发明公开
    METHOD OF MANUFACTURING A SILICON BIPOLAR JUNCTION TRANSISTOR, AND A BJT 审中-公开

    公开(公告)号：US20240234552A1

    公开(公告)日：2024-07-11

    申请号：US18527890

    申请日：2023-12-04

    申请人： NXP B.V.

    发明人： Jay Paul John ,  Patrick Sebel ,  James Albert Kirchgessner

    IPC分类号： H01L29/737 ,  H01L29/165 ,  H01L29/66

    CPC分类号： H01L29/7371 ,  H01L29/165 ,  H01L29/66242

    摘要： Disclosed is a method of manufacturing a silicon bipolar junction transistor device, the method comprising a sequence of steps including: depositing a polysilicon layer over at least a device region; depositing a dielectric layer over the polysilicon layer; patterning a photoresist layer and etching a window in the dielectric layer and the polysilicon layer through an opening in the photoresist layer; etching a SiGe layer stack through the window, to expose a silicon layer thereunder; patterning a further photoresist layer to expose at least the window; and doping the silicon layer by ion implantation through the window to form a base region. A corresponding BJT device is also disclosed.