公开(公告)号：US20250072024A1

公开(公告)日：2025-02-27

申请号：US18237195

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alvin J. Joseph ,  Mark D. Levy ,  Rajendran Krishnasamy ,  Johnatan A. Kantarovsky ,  Ajay Raman ,  Ian A. McCallum-Cook

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/45 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.

公开(公告)号：US20250063801A1

公开(公告)日：2025-02-20

申请号：US18934223

申请日：2024-10-31

Applicant: Innolux Corporation

Inventor： Chin-Lung Ting ,  Jen-Hai Chi ,  Chia-Ping Tseng ,  Chen-Lin Yeh ,  Chung-Kuang Wei ,  Cheng-Hsu Chou

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/93

Abstract: The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.

公开(公告)号：US20250063754A1

公开(公告)日：2025-02-20

申请号：US18803043

申请日：2024-08-13

Applicant: Fujitsu Limited

Inventor： Kenji HOMMA ,  Atsushi YAMADA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: a semiconductor device includes: a channel layer that includes a first nitride semiconductor; a barrier layer provided on a first surface side of the channel layer and includes a second nitride semiconductor; a source electrode and a drain electrode provided on a second surface side opposite to the channel layer side, of the barrier layer; a gate electrode provided between the source electrode and the drain electrode, on the second surface side of the barrier layer; and a polarization layer that is provided between the gate electrode and the drain electrode, from among between the gate electrode and the source electrode and between the gate electrode and the drain electrode on the second surface side of the barrier layer, includes a third nitride semiconductor that contains Al, and has an Al composition that decreases from the barrier layer side toward a third surface side opposite to the barrier layer side.

公开(公告)号：US12230699B2

公开(公告)日：2025-02-18

申请号：US17067988

申请日：2020-10-12

Applicant: Analog Devices, Inc.

Inventor： Daniel Piedra ,  James G. Fiorenza ,  Puneet Srivastava

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

Abstract: Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.

公开(公告)号：US12230690B2

公开(公告)日：2025-02-18

申请号：US18360694

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L29/267 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778

Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

公开(公告)号：US20250056878A1

公开(公告)日：2025-02-13

申请号：US18929367

申请日：2024-10-28

Applicant: MONDE Wireless Inc.

Inventor： Matthew GUIDRY ,  Brian ROMANCZYK

IPC: H01L27/095 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

Abstract: A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits of the front end can include N-polar III-N transistors that are all formed from the same epitaxial material structure and monolithically integrated onto a single chip. Due to the different performance requirements of the various transistors in the different circuits, parameters such as gate length, gate-to-channel separation, and surface-to-channel separation in the access regions of the devices can be varied to meet the desired performance requirements.

公开(公告)号：US20250056826A1

公开(公告)日：2025-02-13

申请号：US18429925

申请日：2024-02-01

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Yosuke KAJIWARA ,  Hiroshi ONO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a first insulating member, and a second insulating member. The first to third electrodes extend along a first direction. The third electrode includes a first electrode portion. The first semiconductor member includes Alx1Ga1-x1N (0≤x1

公开(公告)号：US20250054766A1

公开(公告)日：2025-02-13

申请号：US18772359

申请日：2024-07-15

Applicant: Infineon Technologies Austria AG

Inventor： Clemens Ostermaier ,  Nicholas Dellas

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778

Abstract: A method includes: providing a Group III nitride-based substrate having a first major surface and a doped Group III nitride region; forming a first passivation layer configured as a hydrogen diffusion barrier on the first major surface; forming a first opening in the first passivation layer and exposing at least a portion of the doped Group III nitride region from the first passivation layer; activating a first doped Group III nitride region whilst the first passivation layer is located on the first major surface and the doped Group III nitride region is at least partly exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the doped Group III nitride region; forming a second opening in the first and second passivation layers and exposing a portion of the doped Group III nitride region; and forming a contact in the second opening.

公开(公告)号：US12224339B2

公开(公告)日：2025-02-11

申请号：US17735100

申请日：2022-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

公开(公告)号：US20250048669A1

公开(公告)日：2025-02-06

申请号：US18924109

申请日：2024-10-23

Applicant: Texas Instruments Incorporated

Inventor： Nicholas S. DELLAS ,  Qhalid Fareed RANGOON SAYEED

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

Abstract: In some examples, a gallium-based device comprises a substrate layer; a first group-III nitride layer supported by the substrate layer; a second group-III nitride layer supported by the first group-III nitride layer; a tunnel barrier layer supported by the second group-III nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-III nitride layer.