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    DISPLAY PANEL
    2.
    发明申请
    DISPLAY PANEL 有权

    公开(公告)号：US20250072093A1

    公开(公告)日：2025-02-27

    申请号：US17925002

    申请日：2022-11-07

    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

    Inventor： Zhifu LI ,  Guanghui LIU ,  Fei AI ,  Dewei SONG ,  Zhuang LI

    IPC: H01L29/45 ,  H01L29/49 ,  H01L29/786

    Abstract: A display panel is provided. The display panel includes a substrate and includes a first ohmic contact structure, a first boss, a second ohmic contact structure, a semiconductor structure, and a gate which are stacked on the substrate. The first boss includes at least one sidewall. By arranging the semiconductor structure on the sidewall of the first boss, a length of a channel can be shortened by using an existing technology, and a dimension of a thin film transistor can be reduced, so that an integration level of the thin film transistor in the display panel can be improved.

    SEMICONDUCTOR STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250072072A1

    公开(公告)日：2025-02-27

    申请号：US18940988

    申请日：2024-11-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Meng-Hsuan HSIAO ,  Winnie Victoria Wei-Ning CHEN ,  Tung Ying LEE

    IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/786

    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a first transistor over a substrate, including a first channel layer over the substrate, a second channel layer over and spaced apart from the first channel layer in a first direction, and a first source/drain structure attached to the first channel layer and the second channel layer. The semiconductor structure further includes a second transistor over the substrate, including a third channel layer over the substrate, a fourth channel layer over and spaced apart from the third channel layer in the first direction, and a second source/drain structure attached to the third channel layer and the fourth channel layer. In addition, a dimension of the first source/drain structure in the first direction is different from a dimension of the second source/drain structure in the first direction.

    Thin Film Transistor and Display Apparatus Comprising the Same
    5.
    发明申请
    Thin Film Transistor and Display Apparatus Comprising the Same 有权

    公开(公告)号：US20250072056A1

    公开(公告)日：2025-02-27

    申请号：US18946627

    申请日：2024-11-13

    Applicant: LG Display Co., Ltd.

    Inventor： Sunggu Kim ,  DaeHwan Kim

    IPC: H01L29/786 ,  H01L29/24

    Abstract: A thin film transistor and a display apparatus comprising the same are provided, in which the thin film transistor comprises an active layer, a barrier layer on the active layer; a gate insulating layer on the barrier layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps at least a portion of the active layer, and the barrier layer includes an oxide semiconductor material and has a resistivity greater than a resistivity of the active layer and has a thickness less than a thickness of the active layer.

    SEMICONDUCTOR DEVICES
    6.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250072053A1

    公开(公告)日：2025-02-27

    申请号：US18947664

    申请日：2024-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MYUNG GIL KANG ,  DONG WON KIM ,  WOO SEOK PARK ,  KEUN HWI CHO ,  SUNG GI HUR

    IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

    Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250072048A1

    公开(公告)日：2025-02-27

    申请号：US18668778

    申请日：2024-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjin YANG ,  Kyunam PARK ,  Jaeho JEON ,  Kyoungmi PARK

    IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes an insulating base layer, a plurality of semiconductor patterns stacked on the insulating base layer and spaced apart from each other, a gate structure surrounding the plurality of semiconductor patterns, first and second source/drain patterns disposed on the insulating base layer and connected to both side surfaces of the plurality of semiconductor patterns, respectively, a contact structure connected to first source/drain patterns through the insulating base layer, a sidewall insulating film disposed between an upper portion of the contact structure and an upper portion of the insulating base layer and extending onto a region of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns, and a power transmission line disposed on a lower surface of the insulating base layer and connected to the contact structure.

    Source/drain features with improved strain properties
    9.
    发明授权
    Source/drain features with improved strain properties 有权

    公开(公告)号：US12237414B2

    公开(公告)日：2025-02-25

    申请号：US17314815

    申请日：2021-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

    IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

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