公开(公告)号：US20240363765A1

公开(公告)日：2024-10-31

申请号：US18306488

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Gerben Doornbos ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Yu-Ming Lin ,  Oreste Madia

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7883 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： Some embodiments relate to an integrated device, including a control gate over a substrate, the control gate having a first length; a tunnel dielectric on the control gate; a floating gate having a second length on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; a channel on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and source/drain terminals on the channel, wherein the first length of the control gate is less than the second length of the floating gate.

公开(公告)号：US12113135B2

公开(公告)日：2024-10-08

申请号：US18174687

申请日：2023-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chu Lin ,  Wen-Chih Chiang ,  Chi-Chung Jen ,  Ming-Hong Su ,  Mei-Chen Su ,  Chia-Wei Lee ,  Kuan-Wei Su ,  Chia-Ming Pan

IPC分类号： H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H10B41/00

CPC分类号： H01L29/788 ,  H01L29/0649 ,  H01L29/42324 ,  H10B41/00

摘要： Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

公开(公告)号：US20240332383A1

公开(公告)日：2024-10-03

申请号：US18739336

申请日：2024-06-11

申请人： United Microelectronics Corp.

发明人： Liang Yi ,  Chi Ren

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

摘要： A method for forming a semiconductor memory device is disclosed. A substrate is provided. A pair of floating gates are formed on the substrate. A recessed region is formed in the substrate between the floating gates, wherein an upper surface of the recessed region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates. A source line doped region is formed in the recessed region. An erase gate is formed between the floating gates and on the recessed region, and a word line is formed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate. A bit line doped region is formed in the substrate and adjacent to the word line.

公开(公告)号：US12108606B2

公开(公告)日：2024-10-01

申请号：US17892514

申请日：2022-08-22

申请人： SK hynix Inc.

发明人： Jae Hyun Han ,  Jae Gil Lee ,  Hyangkeun Yoo ,  Se Ho Lee

IPC分类号： H10B51/20 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H10B51/10

CPC分类号： H10B51/20 ,  H01L29/7827 ,  H01L29/78391 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7889 ,  H10B51/10

摘要： A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US12100611B2

公开(公告)日：2024-09-24

申请号：US18389577

申请日：2023-11-14

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

公开(公告)号：US12096629B2

公开(公告)日：2024-09-17

申请号：US18344161

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Ling Shih ,  Yong-Shiuan Tsair

IPC分类号： H01L29/423 ,  G11C29/14 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/42

CPC分类号： H10B41/42 ,  G11C29/14 ,  H01L21/31116 ,  H01L21/32137 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H01L29/66545

摘要： Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.

公开(公告)号：US12096623B2

公开(公告)日：2024-09-17

申请号：US17309775

申请日：2019-04-09

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC分类号： H10B41/27 ,  H01L29/423 ,  H01L29/788

CPC分类号： H10B41/27 ,  H01L29/42324 ,  H01L29/788

摘要： Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US20240297226A1

公开(公告)日：2024-09-05

申请号：US18660728

申请日：2024-05-10

申请人： Winbond Electronics Corp.

发明人： Che-Jui HSU ,  Ying-Fu TUNG

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/40114 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor structure is provided. The semiconductor structure includes a pad layer, a first conductive layer, a second conductive layer, an interlayer dielectric layer, and a control gate. The pad layer is disposed on a substrate. The first conductive layer is disposed on the pad layer. The second conductive layer is disposed on the first conductive layer. The interlayer dielectric layer is disposed on the first conductive layer and the second conductive layer and is in contact with top surfaces of the first conductive layer and the second conductive layer. The control gate is disposed on the interlayer dielectric layer.

公开(公告)号：US12080592B2

公开(公告)日：2024-09-03

申请号：US17250835

申请日：2019-09-10

申请人： Lam Research Corporation

发明人： Hui-Jung Wu ,  Bart J. van Schravendijk ,  Mark Naoshi Kawaguchi ,  Gereng Gunawan ,  Jay E. Uglow ,  Nagraj Shankar ,  Gowri Channa Kamarthy ,  Kevin M. McLaughlin ,  Ananda K. Banerji ,  Jialing Yang ,  John Hoang ,  Aaron Lynn Routzahn ,  Nathan Musselwhite ,  Meihua Shen ,  Thorsten Bernd Lill ,  Hao Chi ,  Nicholas Dominic Altieri

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L29/788 ,  H10B41/20 ,  H10B41/35

CPC分类号： H01L21/76846 ,  H01L21/0217 ,  H01L21/02263 ,  H01L21/31105 ,  H01L21/76816 ,  H01L29/7889 ,  H10B41/20 ,  H10B41/35

摘要： Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.

公开(公告)号：US12079415B2

公开(公告)日：2024-09-03

申请号：US17963125

申请日：2022-10-10

申请人： Micron Technology, Inc.

发明人： Pankaj Sharma

IPC分类号： G06F3/041 ,  G06F3/01 ,  G06F3/0481 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/04883 ,  G06F3/04886 ,  G06Q10/10 ,  G11B27/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H04L65/403 ,  H04N21/00 ,  H04N21/472 ,  H04N21/84 ,  H04N21/854

CPC分类号： G06F3/0416 ,  G06F3/0481 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/04883 ,  G06F3/04886 ,  G06Q10/10 ,  H01L29/24 ,  H01L29/42324 ,  H01L29/7827 ,  H01L29/78391 ,  H01L29/7889 ,  H04L65/403 ,  H04N21/47205 ,  H04N21/854 ,  G06F3/01 ,  G06F2203/04105 ,  G06F2203/04803 ,  G06F2203/04808 ,  G11B27/10 ,  H04N21/00 ,  H04N21/84

摘要： Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.