公开(公告)号：US20250056818A1

公开(公告)日：2025-02-13

申请号：US18367467

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a bottom portion, a middle portion, a top portion, and a base portion between the bottom portion and the substrate. Preferably, the bottom portion is surrounded by a shallow trench isolation (STI), a gate oxide layer is disposed on the fin-shaped structure and the STI, a bottom surface of the gate oxide layer is higher than a top surface of the base portion, a width of a top surface of the bottom portion is greater than half the width of the bottom surface of the bottom portion, and a tip of the top portion includes a tapered portion.

公开(公告)号：US12218257B2

公开(公告)日：2025-02-04

申请号：US17452394

申请日：2021-10-26

Applicant: Realtek Semiconductor Corporation

Inventor： Jian Liu

IPC: H01L29/94 ,  H01L23/522 ,  H01L49/02

Abstract: A capacitor structure, including a transistor structure, a first metal conductive structure and a second metal conductive structure, is provided. The transistor structure includes a first ladder-shaped frame of a polycrystalline silicon layer and multiple first metal strips of a first metal layer. The first ladder-shaped frame is electrically isolated from the multiple first metal strips, and encircles a part of the multiple first metal strips. The first ladder-shaped frame forms a gate of the transistor structure. The multiple first metal strips form a drain and a source of the transistor structure. The first metal conductive structure is substantially overlapped with the first ladder-shaped frame. The second metal conductive structure is electrically connected to the multiple first metal strips, in which the second metal conductive structure is disposed across and electrically isolated from the first ladder-shaped frame and the first metal conductive structure.

公开(公告)号：US20250031393A1

公开(公告)日：2025-01-23

申请号：US18906877

申请日：2024-10-04

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Fu-Chiang KUO

IPC: H01G4/35 ,  H01L21/285 ,  H01L23/532 ,  H01L29/94

Abstract: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.

公开(公告)号：US12200943B2

公开(公告)日：2025-01-14

申请号：US17879432

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei Ting Hsieh ,  Kuen-Yi Chen ,  Yi-Hsuan Chen ,  Yu-Wei Ting ,  Yi Ching Ong ,  Kuo-Ching Huang

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/94 ,  H10B53/30

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

公开(公告)号：US20250014824A1

公开(公告)日：2025-01-09

申请号：US18889659

申请日：2024-09-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung WANG ,  Hsih-Yang CHIU

IPC: H01G4/228 ,  H01G13/00 ,  H01L29/94 ,  H10B12/00

Abstract: A capacitor structure includes a contact layer having first, second, third, fourth and fifth portions arranged from periphery to center, an insulating layer over the contact layer and having an opening exposing the contact layer, a bottom conductive plate in the opening, a dielectric layer conformally on the bottom conductive plate and contacting the second and fourth portions of the contact layer, and a top conductive plate on the dielectric layer. The bottom conductive plate includes first, second and third portions extending along a depth direction of the opening, separated from each other, and contacting the first, third and fifth portions of the contact layer, respectively. The first portion of the bottom conductive plate surrounds the second portion of the bottom conductive plate, and the second portion of the bottom conductive plate surrounds the third portion of the bottom conductive plate.

公开(公告)号：US12170283B2

公开(公告)日：2024-12-17

申请号：US18300563

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/08 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861 ,  H01L29/94

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

公开(公告)号：US12166988B2

公开(公告)日：2024-12-10

申请号：US17652176

申请日：2022-02-23

Applicant: Beijing Bytedance Network Technology Co., Ltd. ,  Bytedance Inc.

Inventor： Hongbin Liu ,  Li Zhang ,  Kai Zhang ,  Tianliang Fu ,  Jizheng Xu ,  Yue Wang

IPC: H01L29/94 ,  H04N19/129 ,  H04N19/176 ,  H04N19/18 ,  H04N19/70

Abstract: Video processing methods, devices, and systems are provided. In one example aspect, a method of video processing includes performing a conversion between a current block of a video and a coded representation of the video. The current block has a width W and a height H and includes an allowable scanning region that includes non-zero transform coefficients that are coded in the coded representation according to a scanning order. The allowable scanning region is restricted to a portion of the current block according to a rule that specifies that a bottom-right corner position of the allowable scanning region is different than a bottom-right corner position of the current block.

公开(公告)号：US12166104B2

公开(公告)日：2024-12-10

申请号：US18357509

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo

IPC: H01L29/76 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02 ,  H03K19/0185

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

公开(公告)号：US12154939B2

公开(公告)日：2024-11-26

申请号：US18360941

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

公开(公告)号：US12137255B2

公开(公告)日：2024-11-05

申请号：US17943269

申请日：2022-09-13

Applicant: Tencent America LLC

Inventor： Jun Tian ,  Chao Huang ,  Xiaozhong Xu ,  Xiang Zhang ,  Shan Liu

IPC: H01L29/94 ,  G06T9/00 ,  G06T15/04 ,  H04N19/124 ,  H04N19/91

Abstract: In a method of processing UV coordinates of a three-dimensional (3D) mesh, the UV coordinates of the 3D mesh are received. The UV coordinates are two-dimensional (2D) texture coordinates that include U coordinates in a first axis and V coordinates in a second axis, and are mapped with vertices of the 3D mesh. The UV coordinates of the 3D mesh are processed based on at least one of a quantization process, a separation process, and a transformation process. The quantization process is configured to convert the UV coordinates into a plurality of indicators. The separation process is configured to separate the UV coordinates into the U coordinates and the V coordinates respectively. The transformation process is configured to convert the UV coordinates from a spatial domain into a transform domain. Compression is performed on the processed UV coordinates after the processing of the UV coordinates.