公开(公告)号：US10290751B2

公开(公告)日：2019-05-14

申请号：US14715614

申请日：2015-05-19

申请人： FUJIFILM CORPORATION

发明人： Seiji Yamashita ,  Toshihiro Ise

IPC分类号： H01L31/08 ,  H01L31/09 ,  H01L31/20 ,  H01L51/00 ,  H01L51/42 ,  H01L27/146 ,  H01L31/115 ,  H01L31/117 ,  H01L31/0256 ,  H01L31/0272

摘要： A radiation detector (10) which has a multilayer structure that includes: a first electrode (34); a second electrode (49) that is disposed so as to face the first electrode; a selenium layer (48) that is disposed between the first electrode and the second electrode and contains amorphous selenium; a first blocking organic layer (38) that is adjacent to the selenium layer, between the first electrode and the selenium layer, and that contains a hole transport material having an electron affinity of 3.7 eV or less; and a second blocking organic layer (37) that is adjacent to the selenium layer, between the second electrode and the selenium layer, and that contains an electron transport material having an ionization potential of 5.9 eV or more. This radiation detector (10) has low dark current, excellent durability, and less afterimages.

公开(公告)号：US10084091B2

公开(公告)日：2018-09-25

申请号：US15594436

申请日：2017-05-12

申请人： Acorn Technologies, Inc.

发明人： Paul A. Clifton ,  R. Stockton Gaines

IPC分类号： H01L31/117 ,  H01L29/78 ,  H01L21/762 ,  H01L29/786 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7849 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/7838 ,  H01L29/7846 ,  H01L29/78603

摘要： An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

公开(公告)号：US09705024B2

公开(公告)日：2017-07-11

申请号：US15107209

申请日：2016-01-26

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Feng Jiang ,  Xingdong Liu ,  Chungchun Lee

IPC分类号： H01L31/102 ,  H01L21/00 ,  H01L31/117 ,  H01L27/146

CPC分类号： H01L31/117 ,  H01L27/14623 ,  H01L27/14632 ,  H01L27/14658 ,  H01L27/14669 ,  H01L27/14676

摘要： The present invention provides an invisible light flat plate detector and a manufacturing method thereof, an imaging apparatus, relates to the field of detection technology, can solve problems that the structure of the invisible light flat plate detector in the prior art is complex and the manufacturing method thereof is tedious. The invisible light flat plate detector of the present invention comprises a plurality of detection units and an invisible light conversion layer provided above the detection units for converting invisible light into visible light, each of the detection units comprising a thin film transistor provided on a substrate, and a first insulation layer, a first electrode, a semiconductor photoelectronic conversion module, a second electrode which are successively provided above the thin film transistor and of which projections on the substrate at least partially overlap with a projection of the thin film transistor on the substrate.

公开(公告)号：US20160356901A1

公开(公告)日：2016-12-08

申请号：US14555463

申请日：2014-11-26

申请人： Lawrence Livermore National Security, LLC

发明人： Qinghui Shao ,  Adam Conway ,  Rebecca J. Nikolic ,  Lars Voss ,  Ishwara B. Bhat ,  Sara E. Harrison

IPC分类号： G01T3/08 ,  H01L31/117

CPC分类号： G01T3/08 ,  H01L31/115 ,  H01L31/117

摘要： In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

摘要翻译： 在一个实施例中，一种装置包括：包括n +掺杂剂或p +掺杂剂的第一层; 本征层形成在第一层之上，本征层包括平面部分和在平面部分上方延伸的柱，腔区限定在柱之间; 以及沉积在柱的周边上的第二层，由此形成涂覆的柱，所述第二层基本上不在涂覆的柱之间的本征层的平面部分上。 当第一层包括p +掺杂剂时，第二层包括n +掺杂剂。 当第一层包括n +掺杂剂时，第二层包括p +掺杂剂。 该装置包括沉积在涂覆的柱之间并且在本征层的平面部分之上的中子敏感材料。 在另外的实施例中，每个柱的上部包括与第二层相同类型的掺杂剂。

公开(公告)号：US09269847B2

公开(公告)日：2016-02-23

申请号：US13832906

申请日：2013-03-15

申请人： Canberra Industries, Inc.

发明人： Kenneth Michael Yocum ,  James F. Colaresi ,  Orren K. Tench

IPC分类号： H01L31/117 ,  G01T1/167 ,  H01L31/08 ,  G01T1/29 ,  H01L31/075

CPC分类号： H01L31/117 ,  G01T1/167 ,  G01T1/2928 ,  H01L31/075 ,  H01L31/085 ,  Y02E10/548

摘要： A small anode germanium well (SAGe well) radiation detector system/method providing for low capacitance, short signal leads, small area bottom-oriented signal contacts, enhanced performance independent of well diameter, and ability to determine radiation directionality is disclosed. The system incorporates a P-type bulk germanium volume (PGEV) having an internal well cavity void (IWCV). The external PGEV and IWCV surfaces incorporate an N+ electrode except for the PGEV external base region (EBR) in which a P+ contact electrode is fabricated within an isolation region. The PGEV structure is further encapsulated to permit operation at cryogenic temperatures. Electrical connection to the SAGe well is accomplished by bonding or mechanical contacting to the P+ contact electrode and the N+ electrode. The EBR of the PGEV may incorporate an integrated preamplifier inside the vacuum housing to minimize the noise and gain change due to ambient temperature variation.

摘要翻译： 公开了一种提供低电容，短信号引线，小面积底部定向信号触点，独立于阱直径的增强性能以及确定辐射方向性的能力的小型阳极锗阱（SAGe well）辐射探测器系统/方法。 该系统包含具有内部井腔空隙（IWCV）的P型体积锗体积（PGEV）。 外部PGEV和IWCV表面包含除了在隔离区域内制造P +接触电极的PGEV外部基极区域（EBR）之外的N +电极。 PGEV结构进一步封装以允许在低温下运行。 通过与P +接触电极和N +电极的接合或机械接触来实现与SAGe阱的电连接。 PGEV的EBR可以在真空壳体内部集成一个前置放大器，以最小化由于环境温度变化引起的噪声和增益变化。

公开(公告)号：US08558341B2

公开(公告)日：2013-10-15

申请号：US13323924

申请日：2011-12-13

申请人： Koichiro Tanaka ,  Fumito Isaka ,  Jiro Nishida

发明人： Koichiro Tanaka ,  Fumito Isaka ,  Jiro Nishida

IPC分类号： H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L31/02363 ,  H01L31/02168 ,  H01L31/02366 ,  H01L31/068 ,  H01L31/0747 ,  H01L31/075 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548

摘要： An object is to provide a photoelectric conversion element with high conversion efficiency. In a photoelectric conversion element with a fine periodic structure on a light-receiving surface side, focus is given to the traveling direction of light that is reflected off another surface. The photoelectric conversion element may be given a structure in which a textured structure that reflects light to the other surface is provided, and light that travels from the light-receiving surface side to the other surface side is reflected so that a component that travels along the photoelectric conversion layer increases. By the distance traveled by the reflected light inside the photoelectric conversion layer increasing, the light that enters the photoelectric conversion element is more easily absorbed by the photoelectric conversion layer and less easily released from the light-receiving surface side, and a photoelectric conversion element with high conversion efficiency can be provided.

摘要翻译： 目的在于提供高转换效率的光电转换元件。 在受光面侧具有微细周期结构的光电转换元件中，对从另一面反射的光的行进方向进行聚焦。 可以给光电转换元件提供将光反射到另一表面的纹理结构，并且从受光面侧行进到另一个表面侧的光被反射，从而沿着 光电转换层增加。 通过光电转换层内的反射光行进的距离增加，进入光电转换元件的光更容易被光电转换层吸收，并且不容易从光接收表面侧释放，并且具有 可以提供高转换效率。

公开(公告)号：US08115269B2

公开(公告)日：2012-02-14

申请号：US12710072

申请日：2010-02-22

申请人： Warren M. Farnworth ,  Jerry M. Brooks

发明人： Warren M. Farnworth ,  Jerry M. Brooks

IPC分类号： H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L25/0657 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.

摘要翻译： 一种制造集成电路封装的技术。 具体地，堆叠的存储器件具有最小的互连。 存储器管芯彼此堆叠并电耦合到衬底。 通孔设置在基板和/或存储器管芯中以便于电连接，而不需要在每个接口之间进行复杂的互连技术。 线键用于完成电路封装。

公开(公告)号：US07944024B2

公开(公告)日：2011-05-17

申请号：US12894609

申请日：2010-09-30

申请人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

发明人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

IPC分类号： H01L31/117

CPC分类号： H01L29/7835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66659

摘要： A semiconductor device is provided which is capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer.

摘要翻译： 提供一种半导体器件，其能够抑制在应变硅层中形成的沟道区域中的电子迁移率的降低。 在半导体衬底上形成的p型硅 - 锗层上形成应变硅层。 应变层的厚度被调整为比不发生失配位错的临界膜厚度更厚。 因此，失配位错发生在应变硅层和硅 - 锗层之间的界面附近。

公开(公告)号：US07405465B2

公开(公告)日：2008-07-29

申请号：US11298331

申请日：2005-12-09

申请人： S. Brad Herner

发明人： S. Brad Herner

IPC分类号： H01L31/117

CPC分类号： H01L45/08 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/161 ,  H01L29/165 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.

摘要翻译： 在沉积的硅中，诸如磷和砷的n型掺杂剂倾向于寻求硅的表面，随着层的沉积而上升。 当在没有提供n型掺杂剂的n掺杂硅上沉积第二未掺杂或p掺杂的硅层时，该第二硅层的第一厚度倾向于包括从较低水平扩散的不期望的n型掺杂剂。 当锗与硅合金化时，这种表面寻找行为减弱。 在一些设备中，对于第二层可能不是有利的具有显着的锗含量。 在本发明中，沉积第一重n掺杂的半导体层（优选至少10原子％的锗），随后是几乎没有或没有n型掺杂剂的硅 - 锗覆盖层，之后是几乎没有或没有 n型掺杂剂和少于10at％的锗。 第一层和覆盖层中的锗使n型掺杂剂的扩散最小化到上述的锗贫层中。

公开(公告)号：US20080099882A1

公开(公告)日：2008-05-01

申请号：US11553333

申请日：2006-10-26

申请人： Darwin G. Enicks

发明人： Darwin G. Enicks

IPC分类号： H01L31/117 ,  H01L21/302

CPC分类号： H01L21/30608 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02579 ,  H01L21/0262 ,  Y10S438/933

摘要： A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer is a silicon-germanium layer having a ratio of silicon to germanium of about 50:1 or less, a boron layer formed within the silicon-germanium layer where the boron layer has a full-width half-maximum (FWHM) thickness value of less than 50 nanometers, and a carbon layer formed within the silicon-germanium layer where the carbon layer has an FWHM thickness value of less than 50 nanometers. A ratio of boron to carbon in the etch-stop layer is in a range of about 0.5 to 1.5.

摘要翻译： 一种用于形成蚀刻停止层的方法和由其制成的所得结构。 蚀刻停止层是具有约50:1或更小的硅与锗的比率的硅 - 锗层，在硅 - 锗层内形成的硼层，其中硼层具有全宽半最大值（FWHM ）厚度值小于50纳米，以及形成在硅 - 锗层内的碳层，其中碳层的FWHM厚度值小于50纳米。 蚀刻停止层中的硼与碳的比例在约0.5至1.5的范围内。