公开(公告)号：US12132075B2

公开(公告)日：2024-10-29

申请号：US17412456

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Wen Hsu ,  Jiech-Fun Lu ,  Li-Weng Chang

IPC分类号： H01L29/06 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L28/20 ,  H01L21/31116 ,  H01L21/32134 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688

摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.

公开(公告)号：US12132043B2

公开(公告)日：2024-10-29

申请号：US18119260

申请日：2023-03-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC分类号： H01L27/06 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC分类号： H01L27/0605 ,  H01L21/30621 ,  H01L21/765 ,  H01L21/8252 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

摘要： A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

公开(公告)号：US12125874B2

公开(公告)日：2024-10-22

申请号：US17647481

申请日：2022-01-10

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kyoungyoon Baek

IPC分类号： H01L23/522 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L28/92

摘要： The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a substrate, a laminated structure, and capacitor units, and the laminated structure includes support layers; forming a first mask layer, wherein the first mask layer covers a top surface of the laminated structure; forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the laminated structure, and a projection region of the first opening on the substrate at least partially overlaps with projection regions of the capacitor units on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening, and the shielding structure covers a sidewall of the first opening.

公开(公告)号：US12125873B2

公开(公告)日：2024-10-22

申请号：US17657641

申请日：2022-04-01

申请人： HeFeChip Corporation Limited

发明人： Liang Li ,  Chunhui Low ,  Huang Liu

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L28/90 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1203 ,  H10B12/056 ,  H10B12/30 ,  H10B12/36 ,  H10B12/37

摘要： A method to form a fin structure on deep trenches (DTs) for a semiconductor device includes the following steps: A buried oxide layer (BOX) having the DTs, and silicon polies in the DTs is provided. A fin on the BOX and the silicon polies having poly fences is provided. A first mask is disposed on the fin. A liner is disposed on the BOX and the first mask, wherein the liner has a first part above the fin, a second part at lateral sides of the fin and a third part on the DTs and the BOX. A second mask is disposed on the first and the second parts of the liner. The second mask and the third parts of the liner are removed to reveal the first and the second parts of the liner. The poly fences are removed and spacers at the lateral sides are formed.

公开(公告)号：US12119414B2

公开(公告)日：2024-10-15

申请号：US18327869

申请日：2023-06-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Fu-Chiang Kuo

IPC分类号： H01L29/94 ,  H01L21/762 ,  H01L29/66 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L28/40 ,  H01L28/75 ,  H01L28/91 ,  H01L29/66181 ,  H10B12/038

摘要： A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.

公开(公告)号：US12119176B2

公开(公告)日：2024-10-15

申请号：US17179890

申请日：2021-02-19

申请人： Micron Technology, Inc.

发明人： Pankaj Sharma ,  Sidhartha Gupta

IPC分类号： H01G11/26 ,  H01G11/08 ,  H01G11/36 ,  H01G11/86 ,  H01L25/00 ,  H01L25/16 ,  H01L49/02 ,  H10B99/00 ,  H01G11/52 ,  H01G11/58

CPC分类号： H01G11/26 ,  H01G11/08 ,  H01G11/36 ,  H01G11/86 ,  H01L25/16 ,  H01L25/50 ,  H01L28/75 ,  H01L28/86 ,  H01L28/88 ,  H10B99/00 ,  H01G11/52 ,  H01G11/58

摘要： Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12114509B2

公开(公告)日：2024-10-08

申请号：US17712495

申请日：2022-04-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Fu-Chen Chang ,  Chih-Hsiang Chang ,  Sheng-Hung Shih

IPC分类号： H01L21/00 ,  G11C11/22 ,  H01L49/02 ,  H10B53/10 ,  H10B53/30

CPC分类号： H10B53/30 ,  G11C11/221 ,  H01L28/56 ,  H01L28/75 ,  H10B53/10

摘要： In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

公开(公告)号：US12114503B2

公开(公告)日：2024-10-08

申请号：US18079039

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC分类号： H10B43/30 ,  H01L21/311 ,  H01L29/66 ,  H01L29/792 ,  H01L49/02 ,  H10B43/27

CPC分类号： H10B43/30 ,  H01L21/31111 ,  H01L28/00 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/27

摘要： Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US12113100B2

公开(公告)日：2024-10-08

申请号：US17509152

申请日：2021-10-25

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Hongmin Wu ,  Yu-Sheng Ting

IPC分类号： H01L29/94 ,  H01L49/02

CPC分类号： H01L28/75 ,  H01L28/92 ,  H01L29/945

摘要： Provided are a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate in which a capacitor structure is formed, and the capacitor structure includes a lower electrode plate, a dielectric layer, an upper electrode plate and a protective layer. The lower electrode plate is located on the substrate. The dielectric layer covers a surface of the lower electrode plate. The upper electrode plate covers the dielectric layer. The protective layer is formed on a surface of the upper electrode plate parallel to the substrate.

公开(公告)号：US12113096B2

公开(公告)日：2024-10-08

申请号：US16585121

申请日：2019-09-27

申请人： FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.

发明人： Tobias Erlbacher

IPC分类号： H01L21/768 ,  H01L49/02

CPC分类号： H01L28/40 ,  H01L21/768

摘要： In a method for producing semiconductor capacitors having different capacitance values on a common substrate, firstly a partially processed semiconductor substrate is produced as a semi-finished product with hole structures and filled with a layer sequence of a dielectric and an electrically conductive layer—independently of the semiconductor capacitors to be produced subsequently. The production of the semiconductor capacitors having different capacitance values only then takes place in a second production phase by corresponding metallization and structuring. The semiconductor capacitors are then separated along dividing regions through which different groups of holes are separated from one another during the production of the semi-finished product. The method enables a more cost-effective production of semiconductor capacitors having different capacitance values in small numbers of items in make-to-order fabrication (foundry process).