Method and system for balancing parallel DC/DC converters

    公开(公告)号:US12107493B2

    公开(公告)日:2024-10-01

    申请号:US17533314

    申请日:2021-11-23

    申请人: LEAR CORPORATION

    IPC分类号: H02M3/04

    CPC分类号: H02M3/04

    摘要: A method and system for balancing output currents of parallel connected first and second DC/DC converters is provided. In operation, the first converter (i) receives, via a communications line connected between the converters such as a CAN bus, a value of the output current of the second converter and (ii) uses this value in weighing an output voltage comparison performed by the first converter for generating the output current of the first converter to thereby adjust the output current of the first converter based on this value. Likewise, the second converter (i) receives, via the communications line, a value of the output current of the first converter and (ii) uses this value in weighing an output voltage comparison performed by the second converter for generating the output current of the second converter to thereby adjust the output current of the second converter based on this value.

    Control for an electromagnetic holding brake

    公开(公告)号:US12021473B2

    公开(公告)日:2024-06-25

    申请号:US17365446

    申请日:2021-07-01

    CPC分类号: H02P3/06 H02M3/04

    摘要: A control for an electromagnetic holding brake with a coil for releasing the holding brake and maintaining it in the released position, which requires a minimum brake coil voltage to maintain it in the re-leased position, having a DC-DC converter with an input and an output, the DC-DC converter being designed to convert a variable input voltage pre-sent at the input into a predetermined switch-on voltage provided at the output and a predetermined holding voltage provided at the output, the holding voltage corresponding to the minimum brake coil voltage, the DC-DC converter being designed to implement a 2-stage voltage control and, in a first stage, to maintain the switch-on voltage as a regulated DC voltage for a predetermined time, to downregulate the voltage from the switch-on voltage following a predetermined voltage curve to the holding voltage as regulated DC voltage, and to maintain it in a second stage.

    METHODS AND EQUIPMENT FOR REDUCING POWER LOSS IN RADIO SYSTEMS

    公开(公告)号:US20240120834A1

    公开(公告)日:2024-04-11

    申请号:US18546072

    申请日:2022-02-14

    发明人: John T. Hanley

    IPC分类号: H02M3/04

    CPC分类号: H02M3/04

    摘要: Methods and systems of powering a radio that can be mounted on a tower of a wireless communication system are provided in which a direct current (“DC”) voltage is provided to the radio over a power cable from a power supply configured to change the direct current (DC) output from the power supply based on a measured current level. The power supply is configured to change the DC voltage from a first voltage level to a second voltage level in response to the measured current being greater than or equal to a first threshold value.

    SYSTEMS AND METHODS FOR ADAPTIVE POWER CONVERTERS

    公开(公告)号:US20240063713A1

    公开(公告)日:2024-02-22

    申请号:US18261080

    申请日:2022-01-11

    发明人: Peter Starek

    IPC分类号: H02M3/04

    CPC分类号: H02M3/04

    摘要: Systems and methods for adaptive power converters are provided. In one embodiment, an adaptive power converter comprises: a power converter controller; a switching power conversion circuit comprising an input switch, a low-pass filter, and a non-linear control feedback compensator, the input switch controlled using feedback control from the non-linear control feedback compensator, wherein the non-linear control feedback compensator controls the input switch to regulate an output from the power conversion circuit based on multiple regulation profiles; a measurement estimate and gain module; and a power converter state detection and correction function. The measurement estimate and gain module evaluates power converter state information from the power converter state detection and correction function. Based on the power converter state information, the measurement estimate and gain module controls the compensator to select a regulation profile, wherein the non-linear control feedback compensator applies the regulation profile for regulating the output from the conversion circuit.

    Submodule for conversion of direct current power and method for updating program for submodule

    公开(公告)号:US11909328B2

    公开(公告)日:2024-02-20

    申请号:US17427388

    申请日:2019-12-30

    发明人: Dong Min Choi

    IPC分类号: G06F1/26 H02M7/483 H02M3/04

    摘要: A submodule for conversion of DC power capable of a plurality thereof being connected in series and used for DC-DC conversion in accordance with the present invention comprises: a power switching element for switching DC power supply to convert a source of DC including voltage transformation; a DC capacitor for storing DC power opened or closed by the power switching element; a power supply unit for supplying power required to drive the submodule from the DC capacitor; a submodule controller for controlling whole operation of the submodule; memory for storing data required for operating the submodule controller; and a communicating unit for performing data communication with an external device; wherein the submodule controller may perform a program update during a start sequence of the submodule or during a stop sequence thereof, while DC-DC conversion is operated.

    Reduction of low frequency noise in a discrete spread spectrum timebase

    公开(公告)号:US11881767B2

    公开(公告)日:2024-01-23

    申请号:US16440509

    申请日:2019-06-13

    发明人: Joerg Erik Goller

    摘要: An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the timebase generator. The timebase generator comprises a first linear feedback shift register (LFSR), a signal generator having an input coupled to an output of the first LFSR; and a digital divider comprising a second LFSR and a programmable digital divider, wherein a clock input of the programmable digital divider is coupled to an output of the signal generator, wherein an output of the programmable digital divider is coupled to a clock input of the first LFSR and is coupled to a clock input of the second LFSR, and wherein an output of the second LFSR is coupled to a program input of the programmable digital divider.