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公开(公告)号：US11616475B2
公开(公告)日：2023-03-28
申请号：US17141726
申请日：2021-01-05
申请人： pSemi Corporation
摘要： Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
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公开(公告)号：US11573556B2
公开(公告)日：2023-02-07
申请号：US17141161
申请日：2021-01-04
发明人： Yu-Wen Wang , Jia-Hua Hong
IPC分类号： H03G1/00 , G05B19/4155 , G01R27/28 , H03G3/00
摘要： A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.
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公开(公告)号：US11569857B2
公开(公告)日：2023-01-31
申请号：US17384518
申请日：2021-07-23
申请人： pSemi Corporation
发明人： Rong Jiang , Khushali Shah , Peter Bacon
摘要： A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
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公开(公告)号：US11463060B2
公开(公告)日：2022-10-04
申请号：US17038988
申请日：2020-09-30
发明人： Yuri Honda , Fumio Harima , Yoshiki Kogushi , Shota Ishihara , Fuminori Morisawa
摘要： The present disclosure provides a power amplifier circuit capable of suppressing the occurrence of noises while enabling control of an output power level. The power amplifier circuit includes a first transistor that amplifies a first signal; a bias circuit that supplies a bias current or voltage based on a control signal to the first transistor; a second transistor to which a control current based on the control signal is supplied, which has an emitter or a source thereof connected to a collector or a drain of the first transistor, and from which a second signal obtained by amplifying the first signal is output; and a first feedback circuit provided between the collector or the drain of the second transistor and the base or the gate of the second transistor.
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公开(公告)号：US20220311403A1
公开(公告)日：2022-09-29
申请号：US17210080
申请日：2021-03-23
摘要： The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.
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公开(公告)号：US11425498B2
公开(公告)日：2022-08-23
申请号：US16990488
申请日：2020-08-11
发明人： Ding Wei
摘要： A method of regulating power supply to a speaker and a system for regulating power supply to a speaker comprising a generating of a low frequency signal output to the speaker, sensing a current and a voltage of the speaker after the low frequency signal is output to the speaker, measuring an impedance of the speaker based on the current and voltage, determining a temperature of the speaker and comparing with a threshold value, and lowering a power supply to the speaker where the temperature is above the threshold value.
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公开(公告)号：US11329621B2
公开(公告)日：2022-05-10
申请号：US17064509
申请日：2020-10-06
发明人： Junhyung Lee , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
摘要： Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using an amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. Individual inputs can be configured to bypass the variable attenuation in a high gain mode.
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公开(公告)号：US20220131474A1
公开(公告)日：2022-04-28
申请号：US17081513
申请日：2020-10-27
发明人： Andrey Malinin , Renato Bessegato , Yong Siang Teo
摘要： A synchronous rectifier includes: an integrator configured to integrate a voltage across a secondary side winding of a transformer over an integral period having an expected zero integral value; a first comparator configured to detect an end of a demagnetization phase of the secondary side winding based on diode detection; and a digital circuit configured to adjust a channel gain of the synchronous rectifier based on an integration error at the end of the integral period, the integration error corresponding to the difference between the integrated voltage at the end of the integral period and the expected zero integral. Corresponding methods of gain tuning and a power converter are also described.
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9.发明申请公开(公告)号：US20220094314A1
公开(公告)日：2022-03-24
申请号：US17544478
申请日：2021-12-07
申请人： SK hynix Inc.
发明人： Ji Hyo KANG
摘要： An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.
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公开(公告)号：US20220014221A1
公开(公告)日：2022-01-13
申请号：US17384518
申请日：2021-07-23
申请人： pSemi Corporation
发明人： Rong Jiang , Khushali Shah , Peter Bacon
摘要： A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
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