-
公开(公告)号：US20230137280A1
公开(公告)日：2023-05-04
申请号：US17863707
申请日：2022-07-13
发明人： Geunyong LEE , Hyunjin YOO
摘要： A gain attenuation circuit that attenuates an input RF signal and transmits the attenuated RF signal to a power transistor is provided. The gain attenuation circuit includes a first diode connected between a first node positioned between a port to which the input RF signal is input and a control terminal of the power transistor, and a ground; a first transistor and a second transistor stacked between a first power source and the ground, and each including a diode-connection structure; and a third transistor configured to receive an operating voltage set by the first transistor and the second transistor through a control terminal, and operate the first diode based on the received operating voltage.
-
公开(公告)号：US20230133223A1
公开(公告)日：2023-05-04
申请号：US17979356
申请日：2022-11-02
发明人： BENG-MENG CHEN , CHIEN-JUNG HUANG , JHIH-YUAN KE
摘要： The present invention discloses a transmission circuit having output power compensation mechanism. A base-band circuit receives and processes a digital input signal to perform conversion and amplification according to at least one gain parameter to generate an analog output signal. A frequency up-converting circuit performs frequency up-conversion on the analog output signal to generate an RF signal. A RF amplification circuit amplifies the RF signal to generate an output RF signal to an antenna. A temperature monitoring circuit monitors temperature of the RF amplification circuit to generate an instant temperature value thereof. A calibration circuit increases at least a part of the gain parameter when the instant temperature value makes a power of the RF amplification circuit decrease and decreases at least a part of the gain parameter when the instant temperature value makes the power increase.
-
公开(公告)号：US20230132419A1
公开(公告)日：2023-05-04
申请号：US17518925
申请日：2021-11-04
申请人： BeRex Inc.
摘要： Radio frequency (RF) power amplifier architectures and circuits providing compensated current and gain from turn-on to end of long signal burst intervals to counteract amplifier transistor thermal rise due to self-heating at turn-on. The RF receiver circuit may be implemented as one of a single chip device or as part of an integrated system of components for use in mobile communication systems.
-
公开(公告)号：US20230128266A1
公开(公告)日：2023-04-27
申请号：US17512552
申请日：2021-10-27
发明人： Arnab DAS
摘要： An apparatus comprises a transistor pair including a first metal oxide semiconductor field effect transistor (MOSFET) coupled to a second MOSFET. The first MOSFET includes a first gate terminal and a first drain terminal. The second MOSFET comprises a second gate terminal and a second drain terminal. The first gate terminal is configured to receive a first signal. The second gate terminal is configured to receive a second signal that is phase shifted with respect to the first signal. An output node is coupled to the first drain terminal and the second drain terminal and configured to output a third signal that is proportional to a power of the first signal and the second signal.
-
5.发明授权公开(公告)号：US11637537B2
公开(公告)日：2023-04-25
申请号：US16938734
申请日：2020-07-24
申请人： INVENSENSE, INC.
发明人： Igor Mucha , Michael Perrott
摘要： Exemplary multipath digital microphones described herein can comprise exemplary embodiments of automatic gain control and multipath digital audio signal digital signal processing chains, which allow low power and die size to be achieved as described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can facilitate switching between multipath digital audio signal digital signal processing chains while minimizing audible artifacts associated with either the change in the gain automatic gain control amplifiers switching between multipath digital audio signal digital signal processing chains.
-
公开(公告)号：US11637535B2
公开(公告)日：2023-04-25
申请号：US17367624
申请日：2021-07-06
IPC分类号： H03F1/22 , H03F3/191 , H03F1/32 , H03F1/56 , H03F1/02 , H03F3/24 , H04L25/02 , H04B1/04 , H04L27/04 , H03F3/19 , H03F3/21 , H04B1/40 , H03F1/30 , H03G3/30
摘要： The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.
-
公开(公告)号：US11636841B2
公开(公告)日：2023-04-25
申请号：US16835750
申请日：2020-03-31
申请人： Bose Corporation
IPC分类号： G10K11/178 , H03G3/30 , H04R1/10 , H03G3/32 , H04R3/00
摘要： The technology described in this document can be embodied in a method that includes receiving an input signal captured by one or more sensors associated with an active noise reduction (ANR) headphone, and determining one or more characteristics of a first portion of the input signal. Based on the one or more characteristics of the first portion of the input signal, a gain of a variable gain amplifier (VGA) disposed in an ANR signal flow path can be adjusted, and accordingly, a set of coefficients for a tunable digital filter disposed in the ANR signal flow path can be selected. The method further includes processing a second portion of the input signal in the ANR signal flow path using the adjusted gain and selected set of coefficients to generate a second output signal for the electroacoustic transducer of the ANR headphone.
-
公开(公告)号：US20230119349A1
公开(公告)日：2023-04-20
申请号：US18084172
申请日：2022-12-19
IPC分类号： H03K5/13 , G11C11/22 , G11C11/4076 , H03G3/30 , H03F3/45
摘要： Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.
-
公开(公告)号：US20230100245A1
公开(公告)日：2023-03-30
申请号：US17448822
申请日：2021-09-24
摘要： An integrated circuit includes a transimpedance amplifier and an injection circuit. The injection circuit generates a first electrical test signal and injects the first electrical test signal into the transimpedance amplifier. The first electrical test signal or an output of the transimpedance amplifier generated based on the first electrical test signal is used to determine whether the integrated circuit is faulty.
-
公开(公告)号：US20230099576A1
公开(公告)日：2023-03-30
申请号：US17490771
申请日：2021-09-30
发明人： Jianjun Jiang , Daniel Zahi Abawi , Guijun Zhang , Chang Lv , Shijia Guo
摘要： An interface circuit includes an input circuit. The input circuit includes a first input pin, a second input pin and a third input pin. The input circuit further includes a first operational amplifier including a first output pin, a first non-inverting input pin electrically coupled to the first input pin via a first impedance and a first switch, and a first inverting input pin coupled to the first output pin. The input circuit also includes a second operational amplifier including a second output pin, a second non-inverting input electrically coupled to the second input pin via a second impedance and a second inverting input pin electrically coupled to the third input pin via a third impedance and a second switch. The first input pin and the second input pin are electrically coupled via a third switch and a fourth impedance.
-
-
-
-
-
-
-
-
-
搜索结果
5465 条记录 (耗时 0.051 秒)