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公开(公告)号：US20230139444A1
公开(公告)日：2023-05-04
申请号：US17918844
申请日：2021-04-20
发明人： Yuan Yik KOK , Christian KOSCHEL , Christian RUFF , Markus LOOSER
IPC分类号： H03K17/955 , H03K17/96 , B25F5/00
摘要： A hand-held machine tool (1) including a drive device (4) by which a tool that can be brought into operative connection with the machine tool (1) can be actuated, with a control device (8) for actuating the drive device (4) and at least one capacitive sensor element (30, 35) operatively connected to the control device (8) being provided. The at least one element (2, 75) of the machine tool that is arranged in the region of the capacitive sensor element (30, 35) is grounded.
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公开(公告)号：US20230139374A1
公开(公告)日：2023-05-04
申请号：US18090555
申请日：2022-12-29
发明人： Hyeongnam Kim , Alain Charles , Mohamed Imam , Qin Lei , Chunhui Liu
IPC分类号： H03K17/687 , H01L29/778
摘要： In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V.
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公开(公告)号：US20230139164A1
公开(公告)日：2023-05-04
申请号：US17712028
申请日：2022-04-01
发明人： Yong Liao
IPC分类号： H03K17/693 , H02J50/40 , H02J50/12 , H02J50/80 , H03K17/687 , H03K17/567
摘要： An integrated circuit is described. This integrated circuit may include a wireless-charger transmitter, which includes a driver circuit electrically coupled to multiple branches associated with multiple transmission coils. A given branch may include or may be electrically coupled to: a capacitor, a multiplexor (MUX) switch that includes a single field-effect transistor (FET) or a single integrated-gate bipolar transistor (IGBT), and a given transmission coil. Moreover, the wireless-charger transmitter may include a control circuit that provides control signals to gates of FETs or the IGBTs in the branches that selectively activate at least the MUX switch in the given branch and selectively deactivate remaining MUX switches in a remainder of the branches. Furthermore, the driver circuit may perform wireless charging by driving the given transmission coil in the activated given branch using an electrical signal having a fundamental frequency component.
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公开(公告)号：US20230137936A1
公开(公告)日：2023-05-04
申请号：US17918314
申请日：2021-04-16
发明人： Ronald HOGERVORST , Joseph DUIGAN , Karl RINNE
IPC分类号： H02M3/335 , H02M7/217 , H02M1/08 , H03K17/0412
摘要： An isolated gate driver includes a transformer including primary and secondary windings, a synchronous rectifier connected between the secondary winding and an output terminal of the isolated gate driver, a first switch including a first terminal connected to a supply voltage, a second switch including a first terminal connected to the supply voltage, a first damping resistance connected between a first terminal of the secondary winding and a second terminal of the first switch, a second damping resistance connected between a second terminal of the secondary winding and a second terminal of the second switch, a first inverter including an input connected to the first terminal of the secondary winding and an output connected to a gate terminal of the first switch, and a second inverter including an input connected to the second terminal of the secondary winding and an output connected to a gate terminal of the second switch.
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公开(公告)号：US20230135657A1
公开(公告)日：2023-05-04
申请号：US18146789
申请日：2022-12-27
摘要： A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
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公开(公告)号：US20230135422A1
公开(公告)日：2023-05-04
申请号：US17515034
申请日：2021-10-29
IPC分类号： H03K19/0185 , H03K3/037
摘要： An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
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公开(公告)号：US20230133933A1
公开(公告)日：2023-05-04
申请号：US17880828
申请日：2022-08-04
发明人： YUAN-SHENG LEE , YAO-CHIA LIU
IPC分类号： H03K5/135
摘要： A phase interpolator includes phase interpolator circuitries. The phase interpolator circuitries generate an output clock signal from an output node according to phase control bits and clock signals. Phases of the clock signals are different from each other. Each phase circuitry includes phase buffer circuits. Each phase buffer circuit is turned on according a first bit and a second bit of the phase control bits, in order to generate a signal component in the output clock signal according to a corresponding clock signal of the clock signals. Each phase buffer circuit includes a first resistor and a second resistor, and transmits one of a first voltage and a second voltage to the output node according to the corresponding clock signal, in which the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.
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公开(公告)号：US20230133850A1
公开(公告)日：2023-05-04
申请号：US17590584
申请日：2022-02-01
申请人： Arm Limited
IPC分类号： H03K19/0185 , H03K19/003
摘要： Various implementations described herein are directed to a device having an input-output pad configured to receive and supply an input-output pad voltage. The device may include gate tracking circuitry that receives a first voltage, receives a second voltage different than the first voltage, receives node voltages and provides a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the node voltages. The device may include output circuitry that receives the first tracking voltage and the second tracking voltage from the gate tracking circuitry and provides the input-output pad voltage to the input-output pad based on the first tracking voltage and the second tracking voltage.
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9.发明申请公开(公告)号：US20230133268A1
公开(公告)日：2023-05-04
申请号：US17515868
申请日：2021-11-01
申请人： NXP B. V.
发明人： Erik Olieman , Mark Stoopman , Helmut Kranabenter
摘要： A duty cycle correction (DCC) circuit for use in relation to differential signal communications, a method of providing duty cycle correction, and communications systems and methods employing same, are disclosed herein. In one example embodiment, the circuit includes a differential signal inverter circuit including first and second inverter circuits, each of which has a respective inverter and respective first and second transistor devices respectively coupled between the respective inverter and first and second voltages, respectively. The circuit also includes a feedback circuit coupled to respective output ports of the respective first and second inverter circuits and also to respective feedback input ports of the respective transistor devices. The feedback circuit operates to provide one or more feedback signals causing one or more of the transistor devices to perform current limiting. Respective duty cycles of output signals respectively are equal or substantially equal based on the current limiting.
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公开(公告)号：US20230132888A1
公开(公告)日：2023-05-04
申请号：US17974930
申请日：2022-10-27
申请人： Qorvo US, Inc.
发明人： Marcus Granger-Jones , Nadim Khlat
摘要： Group delay determination in a communication circuit is disclosed. The communication circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a power management integrated circuit (PMIC) that generates the modulated voltage. Herein, the PMIC includes a group delay determination circuit to determine a relative group delay between the modulated voltage and a modulated current, which is internal to the power amplifier circuit and unknown to the PMIC, solely based on signals known to the PMIC. The determined relative group delay can help to time align the modulated voltage with the modulated current at the power amplifier circuit to improve error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Further, by determining the relative group delay based on known signals to the PMIC, it is possible to achieve good time alignment between the modulated voltage and the modulated current.
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