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公开(公告)号：US20240313781A1
公开(公告)日：2024-09-19
申请号：US18123160
申请日：2023-03-17
申请人： XILINX, INC.
发明人： Brian C. GAIDE , Sagheer AHMAD , Trevor J. BAUER , Kenneth MA , David P. SCHULTZ , John O'DWYER , Richard W. SWANSON , Bhuvanachandran K. NAIR , Millind MITTAL
IPC分类号： H03K19/17736 , G01R31/317 , H03K19/0175 , H03K19/17796
CPC分类号： H03K19/17744 , G01R31/31701 , H03K19/017581 , H03K19/17796
摘要： Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.
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公开(公告)号：US12095456B2
公开(公告)日：2024-09-17
申请号：US17789757
申请日：2020-12-24
发明人： Vincent Dessard , Aimad Saib
IPC分类号： H03K19/0175 , H02H9/02 , H03K5/24 , H03K19/003 , H03K19/094
CPC分类号： H03K19/017545 , H02H9/02 , H03K5/24 , H03K19/003 , H03K19/09429
摘要： A digital isolator. The digital isolator a logic module for receiving an input signal D, and providing command signals to first and second sawtooth modulators. The first sawtooth modulator can provide a first sawtooth signal at a node A1 having a fast rising edge triggered by a rising edge of a control signal, followed by a slow falling edge, when D equals 1 and having a fast falling edge triggered by a rising edge of a control signal, followed by a slow rising edge, when D equals 0. A second sawtooth modulator provides a second sawtooth signal at node A2, inverted with respect to first sawtooth signal. Isolation capacitors connected to nodes A1 and A2 can be used as isolation barrier and as part of high-pass filters together with dipoles Z1 and Z2.
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公开(公告)号：US20240305297A1
公开(公告)日：2024-09-12
申请号：US18258706
申请日：2020-12-25
发明人： Zhi LI , Jianzhong ZHAO , Yumei ZHOU
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175
摘要： Provided is a signal driving system with a constant slew. The signal driving system with the constant slew includes: a step voltage generation unit configured to provide multiplex arithmetic gradient voltage signals; a multiplexer, wherein an input end of the multiplexer is connected to the step voltage generation unit to receive the multiplex arithmetic gradient voltage signals, and another input end of the multiplexer is connected to a control signal generation unit, and the multiplexer is configured to selectively output the multiplex arithmetic gradient voltage signals under a control of a control signal generated by the control signal generation unit; a voltage following unit connected to the multiplexer, wherein the voltage following unit is configured to serve as an isolation and improve a driving ability; and an output following unit connected to the voltage following unit, wherein the output following unit is configured to drive a subsequently-connected load unit.
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公开(公告)号：US20240235551A9
公开(公告)日：2024-07-11
申请号：US18546347
申请日：2022-01-27
IPC分类号： H03K19/018 , H03K19/0175
CPC分类号： H03K19/01806 , H03K19/017518
摘要： The invention relates to a level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, wherein the level converter has a first transistor with a downstream first resistor, wherein the level converter is configured in such a way that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.
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公开(公告)号：US12028028B2
公开(公告)日：2024-07-02
申请号：US17390560
申请日：2021-07-30
发明人： Zhiwei Dong
CPC分类号： H03F3/085 , H01G4/38 , H03F3/387 , H03F3/45475 , H03F3/45928 , H03K19/017545 , H03F2200/271 , H03F2200/273 , H03F2200/537
摘要： A digital isolator device which includes a first input buffer configured to receive a first differential signal from a transmitter and to provide a second differential signal, the first differential signal being characterized by a first magnitude, the second differential signal being characterized by a second magnitude, the first magnitude being greater than the second magnitude. The device also includes a second input buffer configured to receive a third differential signal from the transmitter and to provide a fourth differential signal, the second input buffer being coupled to the second ground terminal. The device also includes a common-mode circuit coupled to the second differential signal and the fourth differential signal, the common-mode circuit being configured to reduce a common-mode transient voltage, the common-mode transient voltage being associated with a voltage differential between the first ground terminal and the second ground terminal.
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公开(公告)号：US20240195418A1
公开(公告)日：2024-06-13
申请号：US18062828
申请日：2022-12-07
申请人： Xilinx, Inc.
IPC分类号： H03K19/0175 , H03K19/17736 , H03K19/17764 , H03K19/17768
CPC分类号： H03K19/017581 , H03K19/17744 , H03K19/17764 , H03K19/17768
摘要： An integrated circuit (IC) may include a plurality of compute tiles in a data processing array. Each compute tile is configured to perform a data processing function. The IC may include a plurality of interface tiles in the data processing array. The plurality of interface tiles are communicatively linked to the plurality of compute tiles. The IC may include a plurality of programmable stream switches disposed in the plurality of compute tiles and the plurality of interface tiles. The IC may include a functional safety circuit. The functional safety circuit is connected to a selected programmable stream switch of the plurality of programmable stream switches. The functional safety circuit is configured to perform a functional safety function on a plurality of data streams routed to the functional safety circuit from the selected programmable stream switch.
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公开(公告)号：US12009814B2
公开(公告)日：2024-06-11
申请号：US18084799
申请日：2022-12-20
发明人： Chao-Chun Sung , Che-Lun Hsu , Chang-Han Li
IPC分类号： H03K19/0175 , H03K19/017 , H03K19/0185 , H03K19/173 , H03K19/20
CPC分类号： H03K19/017 , H03K19/018507 , H03K19/1737 , H03K19/20
摘要： A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one between a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level between the level of the first input node and a second low supply voltage to a first output node, wherein the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.
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公开(公告)号：US20240154608A1
公开(公告)日：2024-05-09
申请号：US17983300
申请日：2022-11-08
申请人： NXP USA, Inc.
IPC分类号： H03K3/356 , H03K19/0175 , H04L25/03
CPC分类号： H03K3/356 , H03K19/017518 , H04L25/03878
摘要： Embodiments of level shifters are disclosed. In an embodiment, a level shifter includes a transistor connected between an input terminal of the level shifter and an output terminal of the level shifter, a first resistor connected between a first terminal of the transistor and one of the input terminal of the level shifter and the output terminal of the level shifter, a capacitor connected between the input terminal of the level shifter and the output terminal of the level shifter, a current source connected between the output terminal of the level shifter and a fixed voltage, and a resistor divider connected between the first resistor and the output terminal of the level shifter.
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公开(公告)号：US20240137021A1
公开(公告)日：2024-04-25
申请号：US18546347
申请日：2022-01-27
IPC分类号： H03K19/018 , H03K19/0175
CPC分类号： H03K19/01806 , H03K19/017518
摘要： The invention relates to a level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, wherein the level converter has a first transistor with a downstream first resistor, wherein the level converter is configured in such a way that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.
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公开(公告)号：US11942934B2
公开(公告)日：2024-03-26
申请号：US17793764
申请日：2021-04-27
申请人： Robert Bosch GmbH
发明人： Rudolf Ritter
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/0185
CPC分类号： H03K19/018528 , H03K19/0005 , H03K19/0175 , H03K19/017509
摘要： A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.
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