公开(公告)号：US20250069649A1

公开(公告)日：2025-02-27

申请号：US18948537

申请日：2024-11-15

Applicant: CXMT CORPORATION

Inventor： Jia WANG

IPC: G11C11/4096 ,  G11C11/4094 ,  H03K19/20

Abstract: Provided are a read/write circuit, a read/write method, and a memory. The read/write circuit includes: a write driver circuit, configured to: precharge a data line, and write to-be-written data into the data line; and a control circuit, when in a mask write mode, the control circuit being configured to control the write driver circuit to stop precharging the data line after data read and before data write, and when not in the mask write mode, the control circuit being configured to control the write driver circuit to precharge the data line before data write.

公开(公告)号：US20250069645A1

公开(公告)日：2025-02-27

申请号：US18946954

申请日：2024-11-14

Applicant: CXMT CORPORATION

Inventor： Zhiqiang ZHANG

IPC: G11C11/4076 ,  G11C11/408 ,  H03K19/20

Abstract: Provided are a control circuit, a control method, and a memory. The control circuit includes: an input control circuit, configured to generate a first drive control signal and a second drive control signal based on a command/address control signal and a command/address inversion signal; an input processing circuit, configured to generate a first intermediate command/address signal based on the first drive control signal and the second drive control signal when the command/address control signal is in an enabled state, that the circuit is in a power down mode being indicated when the command/address control signal is in the enabled state; and a logic decoding circuit, configured to generate a power down mode exit signal in the power down mode based on the command/address inversion signal and the first intermediate command/address signal.

公开(公告)号：US12231123B2

公开(公告)日：2025-02-18

申请号：US17971700

申请日：2022-10-24

Applicant: International Business Machines Corporation

Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

IPC: H03K19/195 ,  G06F1/10 ,  G06N10/20 ,  G06N10/40 ,  H03K19/20

Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

公开(公告)号：US12224741B2

公开(公告)日：2025-02-11

申请号：US17935811

申请日：2022-09-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yupeng Fan

IPC: H03K17/687 ,  G11C11/4074 ,  H03K19/20

Abstract: A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal.

公开(公告)号：US20250047287A1

公开(公告)日：2025-02-06

申请号：US18792540

申请日：2024-08-01

Applicant: Montage Electronics (Shanghai) Co., Ltd.

Inventor： Qiuyan Zu ,  Gang Yan ,  Yong Wang ,  Pengzhan Zhang

IPC: H03K21/02 ,  H03K3/037 ,  H03K19/20

Abstract: The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.

公开(公告)号：US12212670B2

公开(公告)日：2025-01-28

申请号：US17214588

申请日：2021-03-26

Applicant: Electronics and Telecommunications Research Institute

Inventor： Do-Young Chung ,  Doo-Ho Choi ,  Sok-Joon Lee ,  Seung-Kwang Lee

IPC: H04L9/08 ,  G06F7/72 ,  H03K19/20 ,  H04L9/06

Abstract: Disclosed herein are an apparatus and method for calculating a multiplicative inverse. The apparatus for calculating a multiplicative inverse includes a data input unit for receiving input data, a multiplicative inverse calculation unit for dividing an input degree-8 finite field corresponding to the input data into two first degree-4 finite fields so as to perform Advanced Encryption Standard (AES) encryption on the input data, and for performing a multiplicative inverse calculation on the first degree-4 finite fields in consideration of a circuit depth value (T-Depth) and qubit consumption of quantum gates in a quantum circuit, and a data output unit for outputting result data obtained by performing the multiplicative inverse calculation.

公开(公告)号：US12212317B2

公开(公告)日：2025-01-28

申请号：US18131009

申请日：2023-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US20250015789A1

公开(公告)日：2025-01-09

申请号：US18547480

申请日：2022-07-07

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Chuangming HOU

IPC: H03K5/14 ,  H03K5/19 ,  H03K19/20

Abstract: A delay measuring circuit includes a control oscillation module with its input terminal connected to its output terminal, which sequentially generates a number of time delay signals with a cycle time T after receiving first enable control signal; a target oscillating module receives a second enabling signal delayed by a first preset threshold than the first enabling signal; after the first preset time T1 is disconnected from the ground terminal/power supply terminal, each stage of the target unit in the target oscillating module connects at the second preset time T2. The level of the target unit turns over at first preset time T1, and target unit maintains logic level for second preset time T2; T1+T2=T/2, and N is an odd integer. So leakage current is reduced and mutual influence of the action current between the adjacent two-level target units are avoided, thus improving ring oscillator performance and reliability.

公开(公告)号：US20250014633A1

公开(公告)日：2025-01-09

申请号：US18890760

申请日：2024-09-20

Applicant: CXMT CORPORATION

Inventor： Yinchuan GU

IPC: G11C11/408 ,  H03K19/20

Abstract: A memory is provided in this application, including multiple group regions, a command decoding circuit, and a control circuit. Each group region includes multiple bank groups, and each bank group corresponds to one bank group address. An active instruction is received by the command decoding circuit, and the active instruction is decoded to obtain an active command signal. The bank group address, a row address, and the active command signal are received by the control circuit, and the row address is sent to one of the group regions based on the active command signal and the bank group address.

公开(公告)号：US12184288B2

公开(公告)日：2024-12-31

申请号：US18043096

申请日：2021-08-25

Applicant: ams International AG

Inventor： Josip Mikulic ,  Gregor Schatzberger

IPC: H03K3/0231 ,  H03B5/24 ,  H03K4/94 ,  H03K5/24 ,  H03K19/20

Abstract: An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.